mirror of https://github.com/lnis-uofu/SOFA.git
22986 lines
2.1 MiB
22986 lines
2.1 MiB
# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
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.model multi_enc_decx2x4
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.inputs clock datain(0) datain(1) datain(2) datain(3) datain(4) datain(5) datain(6) datain(7) datain(8) datain(9) datain(10) datain(11) datain(12) datain(13) datain(14) datain(15) datain(16) datain(17) datain(18) datain(19) datain(20) datain(21) datain(22) datain(23) datain(24) datain(25) datain(26) datain(27) datain(28) datain(29) datain(30) datain(31) datain(32) datain(33) datain(34) datain(35) datain(36) datain(37) datain(38) datain(39) datain(40) datain(41) datain(42) datain(43) datain(44) datain(45) datain(46) datain(47) datain(48) datain(49) datain(50) datain(51) datain(52) datain(53) datain(54) datain(55) datain(56) datain(57) datain(58) datain(59) datain(60) datain(61) datain(62) datain(63) datain(64) datain(65) datain(66) datain(67) datain(68) datain(69) datain(70) datain(71) datain(72) datain(73) datain(74) datain(75) datain(76) datain(77) datain(78) datain(79) datain(80) datain(81) datain(82) datain(83) datain(84) datain(85) datain(86) datain(87) datain(88) datain(89) datain(90) datain(91) datain(92) datain(93) datain(94) datain(95) datain(96) datain(97) datain(98) datain(99) datain(100) datain(101) datain(102) datain(103) datain(104) datain(105) datain(106) datain(107) datain(108) datain(109) datain(110) datain(111) datain(112) datain(113) datain(114) datain(115) datain(116) datain(117) datain(118) datain(119) datain(120) datain(121) datain(122) datain(123) datain(124) datain(125) datain(126) datain(127) datain1(0) datain1(1) datain1(2) datain1(3) datain1(4) datain1(5) datain1(6) datain1(7) datain1(8) datain1(9) datain1(10) datain1(11) datain1(12) datain1(13) datain1(14) datain1(15) datain1(16) datain1(17) datain1(18) datain1(19) datain1(20) datain1(21) datain1(22) datain1(23) datain1(24) datain1(25) datain1(26) datain1(27) datain1(28) datain1(29) datain1(30) datain1(31) datain1(32) datain1(33) datain1(34) datain1(35) datain1(36) datain1(37) datain1(38) datain1(39) datain1(40) datain1(41) datain1(42) datain1(43) datain1(44) datain1(45) datain1(46) datain1(47) datain1(48) datain1(49) datain1(50) datain1(51) datain1(52) datain1(53) datain1(54) datain1(55) datain1(56) datain1(57) datain1(58) datain1(59) datain1(60) datain1(61) datain1(62) datain1(63) datain1(64) datain1(65) datain1(66) datain1(67) datain1(68) datain1(69) datain1(70) datain1(71) datain1(72) datain1(73) datain1(74) datain1(75) datain1(76) datain1(77) datain1(78) datain1(79) datain1(80) datain1(81) datain1(82) datain1(83) datain1(84) datain1(85) datain1(86) datain1(87) datain1(88) datain1(89) datain1(90) datain1(91) datain1(92) datain1(93) datain1(94) datain1(95) datain1(96) datain1(97) datain1(98) datain1(99) datain1(100) datain1(101) datain1(102) datain1(103) datain1(104) datain1(105) datain1(106) datain1(107) datain1(108) datain1(109) datain1(110) datain1(111) datain1(112) datain1(113) datain1(114) datain1(115) datain1(116) datain1(117) datain1(118) datain1(119) datain1(120) datain1(121) datain1(122) datain1(123) datain1(124) datain1(125) datain1(126) datain1(127) datain1_0(0) datain1_0(1) datain1_0(2) datain1_0(3) datain1_0(4) datain1_0(5) datain1_0(6) datain1_0(7) datain1_0(8) datain1_0(9) datain1_0(10) datain1_0(11) datain1_0(12) datain1_0(13) datain1_0(14) datain1_0(15) datain1_0(16) datain1_0(17) datain1_0(18) datain1_0(19) datain1_0(20) datain1_0(21) datain1_0(22) datain1_0(23) datain1_0(24) datain1_0(25) datain1_0(26) datain1_0(27) datain1_0(28) datain1_0(29) datain1_0(30) datain1_0(31) datain1_0(32) datain1_0(33) datain1_0(34) datain1_0(35) datain1_0(36) datain1_0(37) datain1_0(38) datain1_0(39) datain1_0(40) datain1_0(41) datain1_0(42) datain1_0(43) datain1_0(44) datain1_0(45) datain1_0(46) datain1_0(47) datain1_0(48) datain1_0(49) datain1_0(50) datain1_0(51) datain1_0(52) datain1_0(53) datain1_0(54) datain1_0(55) datain1_0(56) datain1_0(57) datain1_0(58) datain1_0(59) datain1_0(60) datain1_0(61) datain1_0(62) datain1_0(63) datain1_0(64) datain1_0(65) datain1_0(66) datain1_0(67) datain1_0(68) datain1_0(69) datain1_0(70) datain1_0(71) datain1_0(72) datain1_0(73) datain1_0(74) datain1_0(75) datain1_0(76) datain1_0(77) datain1_0(78) datain1_0(79) datain1_0(80) datain1_0(81) datain1_0(82) datain1_0(83) datain1_0(84) datain1_0(85) datain1_0(86) datain1_0(87) datain1_0(88) datain1_0(89) datain1_0(90) datain1_0(91) datain1_0(92) datain1_0(93) datain1_0(94) datain1_0(95) datain1_0(96) datain1_0(97) datain1_0(98) datain1_0(99) datain1_0(100) datain1_0(101) datain1_0(102) datain1_0(103) datain1_0(104) datain1_0(105) datain1_0(106) datain1_0(107) datain1_0(108) datain1_0(109) datain1_0(110) datain1_0(111) datain1_0(112) datain1_0(113) datain1_0(114) datain1_0(115) datain1_0(116) datain1_0(117) datain1_0(118) datain1_0(119) datain1_0(120) datain1_0(121) datain1_0(122) datain1_0(123) datain1_0(124) datain1_0(125) datain1_0(126) datain1_0(127) datain_0(0) datain_0(1) datain_0(2) datain_0(3) datain_0(4) datain_0(5) datain_0(6) datain_0(7) datain_0(8) datain_0(9) datain_0(10) datain_0(11) datain_0(12) datain_0(13) datain_0(14) datain_0(15) datain_0(16) datain_0(17) datain_0(18) datain_0(19) datain_0(20) datain_0(21) datain_0(22) datain_0(23) datain_0(24) datain_0(25) datain_0(26) datain_0(27) datain_0(28) datain_0(29) datain_0(30) datain_0(31) datain_0(32) datain_0(33) datain_0(34) datain_0(35) datain_0(36) datain_0(37) datain_0(38) datain_0(39) datain_0(40) datain_0(41) datain_0(42) datain_0(43) datain_0(44) datain_0(45) datain_0(46) datain_0(47) datain_0(48) datain_0(49) datain_0(50) datain_0(51) datain_0(52) datain_0(53) datain_0(54) datain_0(55) datain_0(56) datain_0(57) datain_0(58) datain_0(59) datain_0(60) datain_0(61) datain_0(62) datain_0(63) datain_0(64) datain_0(65) datain_0(66) datain_0(67) datain_0(68) datain_0(69) datain_0(70) datain_0(71) datain_0(72) datain_0(73) datain_0(74) datain_0(75) datain_0(76) datain_0(77) datain_0(78) datain_0(79) datain_0(80) datain_0(81) datain_0(82) datain_0(83) datain_0(84) datain_0(85) datain_0(86) datain_0(87) datain_0(88) datain_0(89) datain_0(90) datain_0(91) datain_0(92) datain_0(93) datain_0(94) datain_0(95) datain_0(96) datain_0(97) datain_0(98) datain_0(99) datain_0(100) datain_0(101) datain_0(102) datain_0(103) datain_0(104) datain_0(105) datain_0(106) datain_0(107) datain_0(108) datain_0(109) datain_0(110) datain_0(111) datain_0(112) datain_0(113) datain_0(114) datain_0(115) datain_0(116) datain_0(117) datain_0(118) datain_0(119) datain_0(120) datain_0(121) datain_0(122) datain_0(123) datain_0(124) datain_0(125) datain_0(126) datain_0(127) reset
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.outputs dataout(0) dataout(1) dataout(2) dataout(3) dataout(4) dataout(5) dataout(6) dataout(7) dataout(8) dataout(9) dataout(10) dataout(11) dataout(12) dataout(13) dataout(14) dataout(15) dataout(16) dataout(17) dataout(18) dataout(19) dataout(20) dataout(21) dataout(22) dataout(23) dataout(24) dataout(25) dataout(26) dataout(27) dataout(28) dataout(29) dataout(30) dataout(31) dataout(32) dataout(33) dataout(34) dataout(35) dataout(36) dataout(37) dataout(38) dataout(39) dataout(40) dataout(41) dataout(42) dataout(43) dataout(44) dataout(45) dataout(46) dataout(47) dataout(48) dataout(49) dataout(50) dataout(51) dataout(52) dataout(53) dataout(54) dataout(55) dataout(56) dataout(57) dataout(58) dataout(59) dataout(60) dataout(61) dataout(62) dataout(63) dataout(64) dataout(65) dataout(66) dataout(67) dataout(68) dataout(69) dataout(70) dataout(71) dataout(72) dataout(73) dataout(74) dataout(75) dataout(76) dataout(77) dataout(78) dataout(79) dataout(80) dataout(81) dataout(82) dataout(83) dataout(84) dataout(85) dataout(86) dataout(87) dataout(88) dataout(89) dataout(90) dataout(91) dataout(92) dataout(93) dataout(94) dataout(95) dataout(96) dataout(97) dataout(98) dataout(99) dataout(100) dataout(101) dataout(102) dataout(103) dataout(104) dataout(105) dataout(106) dataout(107) dataout(108) dataout(109) dataout(110) dataout(111) dataout(112) dataout(113) dataout(114) dataout(115) dataout(116) dataout(117) dataout(118) dataout(119) dataout(120) dataout(121) dataout(122) dataout(123) dataout(124) dataout(125) dataout(126) dataout(127) dataout1(0) dataout1(1) dataout1(2) dataout1(3) dataout1(4) dataout1(5) dataout1(6) dataout1(7) dataout1(8) dataout1(9) dataout1(10) dataout1(11) dataout1(12) dataout1(13) dataout1(14) dataout1(15) dataout1(16) dataout1(17) dataout1(18) dataout1(19) dataout1(20) dataout1(21) dataout1(22) dataout1(23) dataout1(24) dataout1(25) dataout1(26) dataout1(27) dataout1(28) dataout1(29) dataout1(30) dataout1(31) dataout1(32) dataout1(33) dataout1(34) dataout1(35) dataout1(36) dataout1(37) dataout1(38) dataout1(39) dataout1(40) dataout1(41) dataout1(42) dataout1(43) dataout1(44) dataout1(45) dataout1(46) dataout1(47) dataout1(48) dataout1(49) dataout1(50) dataout1(51) dataout1(52) dataout1(53) dataout1(54) dataout1(55) dataout1(56) dataout1(57) dataout1(58) dataout1(59) dataout1(60) dataout1(61) dataout1(62) dataout1(63) dataout1(64) dataout1(65) dataout1(66) dataout1(67) dataout1(68) dataout1(69) dataout1(70) dataout1(71) dataout1(72) dataout1(73) dataout1(74) dataout1(75) dataout1(76) dataout1(77) dataout1(78) dataout1(79) dataout1(80) dataout1(81) dataout1(82) dataout1(83) dataout1(84) dataout1(85) dataout1(86) dataout1(87) dataout1(88) dataout1(89) dataout1(90) dataout1(91) dataout1(92) dataout1(93) dataout1(94) dataout1(95) dataout1(96) dataout1(97) dataout1(98) dataout1(99) dataout1(100) dataout1(101) dataout1(102) dataout1(103) dataout1(104) dataout1(105) dataout1(106) dataout1(107) dataout1(108) dataout1(109) dataout1(110) dataout1(111) dataout1(112) dataout1(113) dataout1(114) dataout1(115) dataout1(116) dataout1(117) dataout1(118) dataout1(119) dataout1(120) dataout1(121) dataout1(122) dataout1(123) dataout1(124) dataout1(125) dataout1(126) dataout1(127) dataout1_0(0) dataout1_0(1) dataout1_0(2) dataout1_0(3) dataout1_0(4) dataout1_0(5) dataout1_0(6) dataout1_0(7) dataout1_0(8) dataout1_0(9) dataout1_0(10) dataout1_0(11) dataout1_0(12) dataout1_0(13) dataout1_0(14) dataout1_0(15) dataout1_0(16) dataout1_0(17) dataout1_0(18) dataout1_0(19) dataout1_0(20) dataout1_0(21) dataout1_0(22) dataout1_0(23) dataout1_0(24) dataout1_0(25) dataout1_0(26) dataout1_0(27) dataout1_0(28) dataout1_0(29) dataout1_0(30) dataout1_0(31) dataout1_0(32) dataout1_0(33) dataout1_0(34) dataout1_0(35) dataout1_0(36) dataout1_0(37) dataout1_0(38) dataout1_0(39) dataout1_0(40) dataout1_0(41) dataout1_0(42) dataout1_0(43) dataout1_0(44) dataout1_0(45) dataout1_0(46) dataout1_0(47) dataout1_0(48) dataout1_0(49) dataout1_0(50) dataout1_0(51) dataout1_0(52) dataout1_0(53) dataout1_0(54) dataout1_0(55) dataout1_0(56) dataout1_0(57) dataout1_0(58) dataout1_0(59) dataout1_0(60) dataout1_0(61) dataout1_0(62) dataout1_0(63) dataout1_0(64) dataout1_0(65) dataout1_0(66) dataout1_0(67) dataout1_0(68) dataout1_0(69) dataout1_0(70) dataout1_0(71) dataout1_0(72) dataout1_0(73) dataout1_0(74) dataout1_0(75) dataout1_0(76) dataout1_0(77) dataout1_0(78) dataout1_0(79) dataout1_0(80) dataout1_0(81) dataout1_0(82) dataout1_0(83) dataout1_0(84) dataout1_0(85) dataout1_0(86) dataout1_0(87) dataout1_0(88) dataout1_0(89) dataout1_0(90) dataout1_0(91) dataout1_0(92) dataout1_0(93) dataout1_0(94) dataout1_0(95) dataout1_0(96) dataout1_0(97) dataout1_0(98) dataout1_0(99) dataout1_0(100) dataout1_0(101) dataout1_0(102) dataout1_0(103) dataout1_0(104) dataout1_0(105) dataout1_0(106) dataout1_0(107) dataout1_0(108) dataout1_0(109) dataout1_0(110) dataout1_0(111) dataout1_0(112) dataout1_0(113) dataout1_0(114) dataout1_0(115) dataout1_0(116) dataout1_0(117) dataout1_0(118) dataout1_0(119) dataout1_0(120) dataout1_0(121) dataout1_0(122) dataout1_0(123) dataout1_0(124) dataout1_0(125) dataout1_0(126) dataout1_0(127) dataout_0(0) dataout_0(1) dataout_0(2) dataout_0(3) dataout_0(4) dataout_0(5) dataout_0(6) dataout_0(7) dataout_0(8) dataout_0(9) dataout_0(10) dataout_0(11) dataout_0(12) dataout_0(13) dataout_0(14) dataout_0(15) dataout_0(16) dataout_0(17) dataout_0(18) dataout_0(19) dataout_0(20) dataout_0(21) dataout_0(22) dataout_0(23) dataout_0(24) dataout_0(25) dataout_0(26) dataout_0(27) dataout_0(28) dataout_0(29) dataout_0(30) dataout_0(31) dataout_0(32) dataout_0(33) dataout_0(34) dataout_0(35) dataout_0(36) dataout_0(37) dataout_0(38) dataout_0(39) dataout_0(40) dataout_0(41) dataout_0(42) dataout_0(43) dataout_0(44) dataout_0(45) dataout_0(46) dataout_0(47) dataout_0(48) dataout_0(49) dataout_0(50) dataout_0(51) dataout_0(52) dataout_0(53) dataout_0(54) dataout_0(55) dataout_0(56) dataout_0(57) dataout_0(58) dataout_0(59) dataout_0(60) dataout_0(61) dataout_0(62) dataout_0(63) dataout_0(64) dataout_0(65) dataout_0(66) dataout_0(67) dataout_0(68) dataout_0(69) dataout_0(70) dataout_0(71) dataout_0(72) dataout_0(73) dataout_0(74) dataout_0(75) dataout_0(76) dataout_0(77) dataout_0(78) dataout_0(79) dataout_0(80) dataout_0(81) dataout_0(82) dataout_0(83) dataout_0(84) dataout_0(85) dataout_0(86) dataout_0(87) dataout_0(88) dataout_0(89) dataout_0(90) dataout_0(91) dataout_0(92) dataout_0(93) dataout_0(94) dataout_0(95) dataout_0(96) dataout_0(97) dataout_0(98) dataout_0(99) dataout_0(100) dataout_0(101) dataout_0(102) dataout_0(103) dataout_0(104) dataout_0(105) dataout_0(106) dataout_0(107) dataout_0(108) dataout_0(109) dataout_0(110) dataout_0(111) dataout_0(112) dataout_0(113) dataout_0(114) dataout_0(115) dataout_0(116) dataout_0(117) dataout_0(118) dataout_0(119) dataout_0(120) dataout_0(121) dataout_0(122) dataout_0(123) dataout_0(124) dataout_0(125) dataout_0(126) dataout_0(127)
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.names $false
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.names $true
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1
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.names $undef
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.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$237633
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.subckt logic_0 a=dataout1_0_net_0(108)
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.subckt in_buff A=clock Q=top_0.clock
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain(0) Q=top_0.datain(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1(0) Q=top_0.datain1(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(0) Q=top_1.datain1(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(1) Q=top_1.datain1(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(10) Q=top_1.datain1(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(100) Q=top_1.datain1(100)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(101) Q=top_1.datain1(101)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(102) Q=top_1.datain1(102)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(103) Q=top_1.datain1(103)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(104) Q=top_1.datain1(104)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=datain1_0(105) Q=top_1.datain1(105)
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.attr module_not_derived 00000000000000000000000000000001
|
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|
|
.subckt out_buff A=dataout_net_0(83) Q=dataout(83)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(84) Q=dataout(84)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(85) Q=dataout(85)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(86) Q=dataout(86)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(87) Q=dataout(87)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(88) Q=dataout(88)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(89) Q=dataout(89)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(9) Q=dataout(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(90) Q=dataout(90)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(91) Q=dataout(91)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout1_0_net_0(108) Q=dataout(92)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(93) Q=dataout(93)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(94) Q=dataout(94)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(95) Q=dataout(95)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(96) Q=dataout(96)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(97) Q=dataout(97)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(98) Q=dataout(98)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=dataout_net_0(99) Q=dataout(99)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt in_buff A=reset Q=top_0.reset
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I1 I2=dataout1_0_LUT4_O_I2 I3=dataout1_0_LUT4_O_I3 O=dataout1_0_net_0(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(125)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(26)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(65)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(25)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_9_I3 O=dataout1_0_net_0(59)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_6_I2 O=dataout1_0_net_0(24)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_91_I3 O=dataout1_0_net_0(54)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_9_I3 O=dataout1_0_net_0(123)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(126)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_75_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(81)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(94)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_98_I2 O=dataout1_0_net_0(23)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_6_I2 O=dataout1_0_net_0(56)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(55)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_89_I2 O=dataout1_0_net_0(50)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(71)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(110)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(106)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(43)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_93_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(39)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_91_I3 O=dataout1_0_net_0(22)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(96)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_9_I2 O=dataout1_0_net_0(20)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(64)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(116)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(84)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(48)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_6_I2 O=dataout1_0_net_0(120)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(32)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(112)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(80)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(100)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_9_I2 O=dataout1_0_net_0(16)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_24_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(68)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(52)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(70)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(66)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_7_I2 O=dataout1_0_net_0(117)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(75)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(73)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(74)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(86)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_93_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(35)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(38)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(57)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(42)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(45)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(109)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(107)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(127)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(104)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(111)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(98)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(72)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_89_I2 O=dataout1_0_net_0(114)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_94_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(47)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(62)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(122)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(5) I2=top_0.data_encout1(6) I3=top_0.data_encout1(4) O=dataout1_0_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(93)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(49)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(97)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(90)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(67)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_95_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(89)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_94_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(46)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_75_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_87_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(95)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_70_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(14)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(88)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(102)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(36)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_61_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(91)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(19)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(37)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(103)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(58)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(0) I1=top_0.data_encout1(2) I2=top_0.data_encout1(1) I3=top_0.data_encout1(3) O=dataout1_0_LUT4_O_67_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(79)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_93_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(83)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(0) I2=top_0.data_encout1(2) I3=top_0.data_encout1(3) O=dataout1_0_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(85)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(78)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(0) I1=top_0.data_encout1(3) I2=top_0.data_encout1(1) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_70_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(121)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_94_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(33)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(82)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(113)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(17)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(2) I3=top_0.data_encout1(0) O=dataout1_0_LUT4_O_75_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_89_I2 O=dataout1_0_net_0(18)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(63)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_95_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(41)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_7_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_7_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(77)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(13)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(119)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_95_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(99)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_7_I2 O=dataout1_0_net_0(53)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_87_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(15)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_87_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_87_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_8_I2 O=dataout1_0_net_0(29)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(34)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(0) I2=top_0.data_encout1(2) I3=top_0.data_encout1(1) O=dataout1_0_LUT4_O_89_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_8_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(6) I2=top_0.data_encout1(4) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_8_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_9_I3 O=dataout1_0_net_0(27)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(101)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_91_I3 O=dataout1_0_net_0(118)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(0) I2=top_0.data_encout1(1) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_91_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(115)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(51)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(2) I2=top_0.data_encout1(0) I3=top_0.data_encout1(1) O=dataout1_0_LUT4_O_93_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(40)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(5) I2=top_0.data_encout1(4) I3=top_0.data_encout1(6) O=dataout1_0_LUT4_O_94_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(105)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(2) I2=top_0.data_encout1(0) I3=top_0.data_encout1(3) O=dataout1_0_LUT4_O_95_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_7_I2 O=dataout1_0_net_0(21)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(69)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(87)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(1) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_98_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(61)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(5) I3=top_0.data_encout1(6) O=dataout1_0_LUT4_O_99_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_9_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1(2) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(1) O=dataout1_0_LUT4_O_9_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I1_LUT4_O_I1 I2=dataout1_0_LUT4_O_I1_LUT4_O_I2 I3=dataout1_0_LUT4_O_I1_LUT4_O_I3 O=dataout1_0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(8) I1=dataout1_0_net_0(5) I2=dataout1_0_net_0(66) I3=dataout1_0_net_0(70) O=dataout1_0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(86) I1=dataout1_0_net_0(74) I2=dataout1_0_net_0(73) I3=dataout1_0_net_0(75) O=dataout1_0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=dataout1_0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(42) I1=dataout1_0_net_0(57) I2=dataout1_0_net_0(38) I3=dataout1_0_net_0(35) O=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(104) I1=dataout1_0_net_0(127) I2=dataout1_0_net_0(107) I3=dataout1_0_net_0(45) O=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(114) I1=dataout1_0_net_0(72) I2=dataout1_0_net_0(98) I3=dataout1_0_net_0(111) O=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I2_LUT4_O_I1 I2=dataout1_0_LUT4_O_I2_LUT4_O_I2 I3=dataout1_0_net_0(80) O=dataout1_0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(112) I1=dataout1_0_net_0(48) I2=dataout1_0_net_0(64) I3=dataout1_0_net_0(96) O=dataout1_0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_LUT4_O_9_I2 I1=dataout1_0_LUT4_O_94_I3 I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_61_I2 O=dataout1_0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=top_0.data_encout1(1) I1=dataout1_0_LUT4_O_I3_LUT4_O_I1 I2=dataout1_0_LUT4_O_I3_LUT4_O_I2 I3=dataout1_0_LUT4_O_I3_LUT4_O_I3 O=dataout1_0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_LUT4_O_8_I2 I1=top_0.data_encout1(6) I2=dataout1_0_LUT4_O_6_I2 I3=top_0.data_encout1(0) O=dataout1_0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(25) I1=dataout1_0_net_0(65) I2=dataout1_0_net_0(61) I3=dataout1_0_net_0(101) O=dataout1_0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(69) I1=dataout1_0_net_0(21) I2=dataout1_0_net_0(105) I3=dataout1_0_net_0(40) O=dataout1_0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_2.data_encout1(0) I1=dataout1_LUT4_O_I1 I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_I3 O=dataout1_net_0(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(105)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(39)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(24)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_7_I2 O=dataout1_net_0(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(120)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_83_I3 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(54)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(102)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(78)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(55)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(27)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(114)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(14)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(107)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(83)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(127)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(99)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_75_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(46)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(123)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(43)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(69)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_96_I2 O=dataout1_net_0(103)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(57)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_75_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(126)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(77)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(66)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_83_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(38)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_95_I2 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(62)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(97)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(117)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(36)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(116)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(68)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(67)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_89_I2 O=dataout1_net_0(109)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(115)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(94)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(6) I3=top_2.data_encout1(4) O=dataout1_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(81)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(37)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(70)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(45)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(91)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(35)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(72)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_83_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(118)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(104)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(65)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_7_I2 O=dataout1_net_0(111)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_96_I2 O=dataout1_net_0(23)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_89_I2 O=dataout1_net_0(93)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(73)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(101)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(85)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(110)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(40)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(98)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(6) I2=top_2.data_encout1(5) I3=top_2.data_encout1(4) O=dataout1_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(41)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(47)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(20)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(50)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(15)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(48)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(17)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(32)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(16)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(113)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(33)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(49)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(80)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(112)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(96)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(64)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_64_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(71)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(79)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(82)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_95_I2 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(53)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(56)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(95)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(63)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(75)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(51)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(19)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(3) I2=top_2.data_encout1(1) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_73_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(125)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(0) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(1) O=dataout1_LUT4_O_75_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(122)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(74)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(58)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(100)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_7_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(6) I2=top_2.data_encout1(4) I3=top_2.data_encout1(5) O=dataout1_LUT4_O_7_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(121)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(90)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(86)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(13)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(22)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(3) I1=top_2.data_encout1(0) I2=top_2.data_encout1(1) I3=top_2.data_encout1(2) O=dataout1_LUT4_O_83_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(87)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_85_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(106)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(34)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_89_I2 O=dataout1_net_0(29)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(61)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_89_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_8_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_8_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(21)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(88)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(42)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(25)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(59)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(1) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_93_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(89)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_95_I2 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(52)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_95_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(119)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(3) I1=top_2.data_encout1(2) I2=top_2.data_encout1(1) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_96_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(18)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(3) I2=top_2.data_encout1(0) I3=top_2.data_encout1(1) O=dataout1_LUT4_O_97_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(26)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(0) I2=top_2.data_encout1(3) I3=top_2.data_encout1(1) O=dataout1_LUT4_O_98_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(84)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(4) I2=top_2.data_encout1(5) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_9_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(3) I2=top_2.data_encout1(2) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_9_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(3) I2=top_2.data_encout1(0) I3=top_2.data_encout1(2) O=dataout1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(0) I3=top_2.data_encout1(3) O=dataout1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_2.data_encout1(1) I1=dataout1_LUT4_O_I3_LUT4_O_I1 I2=dataout1_LUT4_O_I3_LUT4_O_I2 I3=dataout1_LUT4_O_I3_LUT4_O_I3 O=dataout1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_net_0(112) I2=dataout1_net_0(96) I3=dataout1_net_0(64) O=dataout1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_net_0(80) I1=dataout1_net_0(49) I2=dataout1_net_0(113) I3=dataout1_net_0(16) O=dataout1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_net_0(32) I1=dataout1_net_0(17) I2=dataout1_net_0(48) I3=dataout1_net_0(1) O=dataout1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_0_LUT4_O_I2 I3=top_1.data_encout(1) O=dataout_0_net_0(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_1_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(127)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_85_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(117)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_85_I2 O=dataout_0_net_0(21)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_86_I2 O=dataout_0_net_0(20)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_87_I2 O=dataout_0_net_0(19)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_88_I2 O=dataout_0_net_0(18)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_89_I2 O=dataout_0_net_0(17)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_90_I2 O=dataout_0_net_0(16)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_1_I0 O=dataout_0_net_0(15)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_2_I0 O=dataout_0_net_0(14)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_3_I0 O=dataout_0_net_0(13)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_4_I0 O=dataout_0_net_0(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_86_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(116)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_5_I0 O=dataout_0_net_0(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_6_I0 O=dataout_0_net_0(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_7_I0 O=dataout_0_net_0(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_8_I0 O=dataout_0_net_0(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_9_I0 O=dataout_0_net_0(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_85_I2 O=dataout_0_net_0(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_86_I2 O=dataout_0_net_0(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_87_I2 O=dataout_0_net_0(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_88_I2 O=dataout_0_net_0(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_89_I2 O=dataout_0_net_0(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_87_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(115)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_88_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(114)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_89_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(113)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_90_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(112)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_1_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(111)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_2_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(110)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_3_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(109)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_4_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(107)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_2_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(126)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_5_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(106)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_6_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(105)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_7_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(104)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_8_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(103)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_9_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(102)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_85_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(101)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_86_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(100)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_87_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(99)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_88_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(98)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_89_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(97)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(0) I1=top_1.data_encout(3) I2=top_1.data_encout(1) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_3_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(125)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_90_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(96)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_1_I0 O=dataout_0_net_0(95)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_2_I0 O=dataout_0_net_0(94)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_3_I0 O=dataout_0_net_0(93)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_4_I0 O=dataout_0_net_0(91)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_5_I0 O=dataout_0_net_0(90)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_6_I0 O=dataout_0_net_0(89)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_7_I0 O=dataout_0_net_0(88)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_8_I0 O=dataout_0_net_0(87)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_9_I0 O=dataout_0_net_0(86)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_4_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(123)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_85_I2 O=dataout_0_net_0(85)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_86_I2 O=dataout_0_net_0(84)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_87_I2 O=dataout_0_net_0(83)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_88_I2 O=dataout_0_net_0(82)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_89_I2 O=dataout_0_net_0(81)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_90_I2 O=dataout_0_net_0(80)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_1_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(79)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_2_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(78)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_3_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(77)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_4_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(75)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(2) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(1) O=dataout_0_LUT4_O_4_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_5_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(122)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_5_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(74)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_6_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(73)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_7_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(72)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_8_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(71)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_9_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(70)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_85_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(69)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_86_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(68)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_87_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(67)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_88_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(66)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_89_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(65)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(0) I1=top_1.data_encout(2) I2=top_1.data_encout(1) I3=top_1.data_encout(3) O=dataout_0_LUT4_O_5_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_6_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(121)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_90_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(64)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_1_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(63)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_2_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(62)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_3_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(61)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_4_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(59)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_5_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(58)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_6_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(57)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_7_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(56)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_8_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(55)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_9_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(54)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(2) I2=top_1.data_encout(0) I3=top_1.data_encout(3) O=dataout_0_LUT4_O_6_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_7_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(120)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_85_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(53)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_86_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(52)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_87_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(51)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_88_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(50)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_89_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(49)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_90_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(48)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_1_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(47)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_2_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(46)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_3_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(45)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_4_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(43)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(0) I2=top_1.data_encout(2) I3=top_1.data_encout(3) O=dataout_0_LUT4_O_7_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_8_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(119)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_5_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(42)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_6_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(41)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_7_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(40)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_8_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(39)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_9_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(38)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_85_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(37)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_85_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_86_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(36)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_86_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_87_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(35)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(2) I2=top_1.data_encout(0) I3=top_1.data_encout(1) O=dataout_0_LUT4_O_87_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_88_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(34)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(0) I2=top_1.data_encout(2) I3=top_1.data_encout(1) O=dataout_0_LUT4_O_88_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_89_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(33)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(2) I3=top_1.data_encout(0) O=dataout_0_LUT4_O_89_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(1) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_8_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_9_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(118)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_90_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(32)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_90_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_1_I0 O=dataout_0_net_0(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_2_I0 O=dataout_0_net_0(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_3_I0 O=dataout_0_net_0(29)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_4_I0 O=dataout_0_net_0(27)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_5_I0 O=dataout_0_net_0(26)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_6_I0 O=dataout_0_net_0(25)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_7_I0 O=dataout_0_net_0(24)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_8_I0 O=dataout_0_net_0(23)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_9_I0 O=dataout_0_net_0(22)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(0) I2=top_1.data_encout(1) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_9_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout_0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout(0) I2=top_1.data_encout(3) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011000000000010
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=top_1.data_encout(6) O=dataout_0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(18)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_3_I2 O=dataout_net_0(49)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(123)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(56)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(80)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(96)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(66)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(70)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_4_I2 O=dataout_net_0(95)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(23)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(78)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(83)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(118)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(111)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_4_I2 O=dataout_net_0(63)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(106)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(100)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(21)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I0 I1=dataout_LUT4_O_119_I1 I2=dataout_LUT4_O_119_I2 I3=dataout_LUT4_O_119_I3 O=dataout_net_0(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I3 O=dataout_LUT4_O_119_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(21) I1=dataout_net_0(106) I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout_LUT4_O_I3 I1=dataout_LUT4_O_81_I3 I2=dataout_LUT4_O_6_I3 I3=dataout_net_0(57) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(96) I1=dataout_net_0(80) I2=dataout_net_0(56) I3=dataout_net_0(48) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(34) I1=dataout_net_0(115) I2=dataout_net_0(84) I3=dataout_net_0(75) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_LUT4_O_80_I3 I1=dataout_LUT4_O_7_I2 I2=dataout_LUT4_O_81_I3 I3=dataout_net_0(100) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout_LUT4_O_I2 I1=dataout_LUT4_O_3_I2 I2=dataout_LUT4_O_81_I3 I3=dataout_net_0(78) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(105) I1=dataout_net_0(74) I2=dataout_net_0(51) I3=dataout_net_0(67) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(125) I1=dataout_net_0(99) I2=dataout_net_0(86) I3=dataout_net_0(81) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(94) I1=dataout_net_0(13) I2=dataout_net_0(55) I3=dataout_net_0(103) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(50) I1=dataout_net_0(5) I2=dataout_net_0(93) I3=dataout_net_0(127) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(68) I1=dataout_net_0(27) I2=dataout_net_0(37) I3=dataout_net_0(59) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(9) I1=dataout_net_0(17) I2=dataout_net_0(29) I3=dataout_net_0(25) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(89) I1=dataout_net_0(10) I2=dataout_net_0(98) I3=dataout_net_0(54) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(58) I1=dataout_net_0(121) I2=dataout_net_0(19) I3=dataout_net_0(31) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(63) I1=dataout_net_0(111) I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout_LUT4_O_I2 I1=dataout_LUT4_O_93_I2 I2=dataout_LUT4_O_98_I3 I3=dataout_net_0(65) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout_net_0(23) I1=dataout_net_0(95) I2=dataout_net_0(70) I3=dataout_net_0(66) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout_net_0(88) I2=dataout_net_0(120) I3=dataout_net_0(112) O=dataout_LUT4_O_119_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout_net_0(72) I1=dataout_net_0(104) I2=dataout_net_0(16) I3=dataout_net_0(64) O=dataout_LUT4_O_119_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(32) I1=dataout_net_0(24) I2=dataout_net_0(40) I3=dataout_net_0(8) O=dataout_LUT4_O_119_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I1_LUT4_O_I0 I1=dataout_LUT4_O_119_I1_LUT4_O_I1 I2=dataout_LUT4_O_119_I1_LUT4_O_I2 I3=dataout_LUT4_O_119_I1_LUT4_O_I3 O=dataout_LUT4_O_119_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(102) I1=dataout_net_0(110) I2=dataout_net_0(119) I3=dataout_net_0(39) O=dataout_LUT4_O_119_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(41) I1=dataout_net_0(14) I2=dataout_net_0(30) I3=dataout_net_0(79) O=dataout_LUT4_O_119_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(97) I1=dataout_net_0(126) I2=dataout_net_0(90) I3=dataout_net_0(91) O=dataout_LUT4_O_119_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(85) I1=dataout_net_0(109) I2=dataout_net_0(73) I3=dataout_net_0(117) O=dataout_LUT4_O_119_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I2_LUT4_O_I0 I1=dataout_LUT4_O_119_I2_LUT4_O_I1 I2=dataout_LUT4_O_119_I2_LUT4_O_I2 I3=dataout_LUT4_O_119_I2_LUT4_O_I3 O=dataout_LUT4_O_119_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(45) I1=dataout_net_0(42) I2=dataout_net_0(52) I3=dataout_net_0(20) O=dataout_LUT4_O_119_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(116) I1=dataout_net_0(114) I2=dataout_net_0(35) I3=dataout_net_0(61) O=dataout_LUT4_O_119_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(87) I1=dataout_net_0(53) I2=dataout_net_0(107) I3=dataout_net_0(26) O=dataout_LUT4_O_119_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(4) I1=dataout_net_0(3) I2=dataout_net_0(33) I3=dataout_net_0(15) O=dataout_LUT4_O_119_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_LUT4_O_119_I3_LUT4_O_I0 I1=dataout_LUT4_O_119_I3_LUT4_O_I1 I2=dataout_LUT4_O_119_I3_LUT4_O_I2 I3=dataout_LUT4_O_119_I3_LUT4_O_I3 O=dataout_LUT4_O_119_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout_net_0(122) I1=dataout_net_0(77) I2=dataout_net_0(71) I3=dataout_net_0(69) O=dataout_LUT4_O_119_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(118) I1=dataout_net_0(123) I2=dataout_net_0(36) I3=dataout_net_0(101) O=dataout_LUT4_O_119_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(43) I1=dataout_net_0(38) I2=dataout_net_0(62) I3=dataout_net_0(47) O=dataout_LUT4_O_119_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout_net_0(113) I1=dataout_net_0(46) I2=dataout_net_0(49) I3=dataout_net_0(18) O=dataout_LUT4_O_119_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(69)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(71)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(77)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(122)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(15)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(33)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(46)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(26)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(107)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_8_I2 O=dataout_net_0(53)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(87)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_86_I2 O=dataout_net_0(61)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(35)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(114)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(116)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(20)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_9_I2 O=dataout_net_0(52)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(113)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(42)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(45)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(117)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(73)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(109)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(85)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(91)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(90)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(126)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(97)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(1) I2=top_2.data_encout(3) I3=top_2.data_encout(0) O=dataout_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(47)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(79)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(14)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_96_I3 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(41)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(39)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_80_I3 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(119)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(110)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_6_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(102)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(40)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(62)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(24)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(32)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(64)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(16)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(104)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(72)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(88)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(120)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_57_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(112)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(38)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(19)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_96_I3 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(121)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_89_I2 O=dataout_net_0(58)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(54)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(98)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(89)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(25)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(29)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(17)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(3) I2=top_2.data_encout(1) I3=top_2.data_encout(2) O=dataout_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(43)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_7_I2 O=dataout_net_0(59)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(37)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(27)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(68)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(127)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(93)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(50)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_80_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(103)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(0) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_7_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(101)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(55)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(3) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(0) O=dataout_LUT4_O_80_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(13)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_81_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(94)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_3_I2 O=dataout_net_0(81)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(86)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(99)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(125)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(1) I1=top_2.data_encout(2) I2=top_2.data_encout(0) I3=top_2.data_encout(3) O=dataout_LUT4_O_86_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(67)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(51)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(74)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_89_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout(1) I1=top_2.data_encout(3) I2=top_2.data_encout(0) I3=top_2.data_encout(2) O=dataout_LUT4_O_8_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(6) I3=top_2.data_encout(4) O=dataout_LUT4_O_8_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(36)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_96_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(105)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(75)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(84)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(115)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(3) I2=top_2.data_encout(1) I3=top_2.data_encout(0) O=dataout_LUT4_O_93_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(34)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(22)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(57)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(1) I2=top_2.data_encout(0) I3=top_2.data_encout(3) O=dataout_LUT4_O_96_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(65)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(6) I2=top_2.data_encout(5) I3=top_2.data_encout(4) O=dataout_LUT4_O_97_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(82)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(6) I2=top_2.data_encout(4) I3=top_2.data_encout(5) O=dataout_LUT4_O_98_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(48)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_99_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(1) I2=top_2.data_encout(3) I3=top_2.data_encout(2) O=dataout_LUT4_O_9_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_9_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(3) I3=top_2.data_encout(1) O=dataout_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(4) I2=top_2.data_encout(5) I3=top_2.data_encout(6) O=dataout_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=top_0.U011.datain(127) D=top_0.data_encin1_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(126) D=top_0.data_encin1_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(117) D=top_0.data_encin1_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(27) D=top_0.data_encin1_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(27) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_100_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(26) D=top_0.data_encin1_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(26) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_101_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(25) D=top_0.data_encin1_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(25) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_102_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(24) D=top_0.data_encin1_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(24) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_103_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(23) D=top_0.data_encin1_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(23) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_104_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(22) D=top_0.data_encin1_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(22) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_105_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(21) D=top_0.data_encin1_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(21) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_106_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(20) D=top_0.data_encin1_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(20) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_107_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(19) D=top_0.data_encin1_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(19) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_108_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(18) D=top_0.data_encin1_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(18) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_109_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(117) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(116) D=top_0.data_encin1_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(17) D=top_0.data_encin1_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(17) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_110_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(16) D=top_0.data_encin1_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(16) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_111_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(15) D=top_0.data_encin1_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(15) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_112_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(14) D=top_0.data_encin1_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(14) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_113_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(13) D=top_0.data_encin1_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(13) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_114_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(12) D=top_0.data_encin1_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(12) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_115_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(11) D=top_0.data_encin1_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(11) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_116_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(10) D=top_0.data_encin1_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(10) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_117_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(9) D=top_0.data_encin1_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(9) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_118_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(8) D=top_0.data_encin1_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(8) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_119_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(116) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(115) D=top_0.data_encin1_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(7) D=top_0.data_encin1_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(7) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_120_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(6) D=top_0.data_encin1_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(6) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_121_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(5) D=top_0.data_encin1_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(5) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_122_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(4) D=top_0.data_encin1_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(4) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_123_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(3) D=top_0.data_encin1_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(3) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_124_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(2) D=top_0.data_encin1_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(2) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_125_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(1) D=top_0.data_encin1_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(1) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_126_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(0) D=top_0.data_encin1_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(0) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_127_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(115) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(114) D=top_0.data_encin1_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(114) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(113) D=top_0.data_encin1_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(113) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(112) D=top_0.data_encin1_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(112) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(111) D=top_0.data_encin1_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(111) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(110) D=top_0.data_encin1_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(110) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(109) D=top_0.data_encin1_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(109) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(108) D=top_0.data_encin1_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(108) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(126) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(125) D=top_0.data_encin1_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(107) D=top_0.data_encin1_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(107) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(106) D=top_0.data_encin1_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(106) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(105) D=top_0.data_encin1_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(105) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(104) D=top_0.data_encin1_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(104) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(103) D=top_0.data_encin1_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(103) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(102) D=top_0.data_encin1_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(102) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(101) D=top_0.data_encin1_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(101) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(100) D=top_0.data_encin1_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(100) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(99) D=top_0.data_encin1_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(99) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(98) D=top_0.data_encin1_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(98) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(125) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(124) D=top_0.data_encin1_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(97) D=top_0.data_encin1_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(97) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(96) D=top_0.data_encin1_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(96) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(95) D=top_0.data_encin1_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(95) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_32_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(94) D=top_0.data_encin1_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(94) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_33_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(93) D=top_0.data_encin1_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(93) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_34_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(92) D=top_0.data_encin1_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(92) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_35_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(91) D=top_0.data_encin1_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(91) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_36_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(90) D=top_0.data_encin1_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(90) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_37_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(89) D=top_0.data_encin1_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(89) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_38_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(88) D=top_0.data_encin1_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(88) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_39_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(124) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(123) D=top_0.data_encin1_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(87) D=top_0.data_encin1_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(87) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_40_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(86) D=top_0.data_encin1_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(86) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_41_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(85) D=top_0.data_encin1_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(85) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_42_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(84) D=top_0.data_encin1_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(84) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_43_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(83) D=top_0.data_encin1_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(83) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_44_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(82) D=top_0.data_encin1_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(82) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_45_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(81) D=top_0.data_encin1_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(81) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_46_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(80) D=top_0.data_encin1_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(80) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_47_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(79) D=top_0.data_encin1_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(79) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_48_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(78) D=top_0.data_encin1_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(78) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_49_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(123) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(122) D=top_0.data_encin1_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(77) D=top_0.data_encin1_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(77) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_50_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(76) D=top_0.data_encin1_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(76) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_51_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(75) D=top_0.data_encin1_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(75) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_52_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(74) D=top_0.data_encin1_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(74) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_53_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(73) D=top_0.data_encin1_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(73) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_54_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(72) D=top_0.data_encin1_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(72) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_55_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(71) D=top_0.data_encin1_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(71) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_56_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(70) D=top_0.data_encin1_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(70) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_57_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(69) D=top_0.data_encin1_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(69) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_58_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(68) D=top_0.data_encin1_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(68) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_59_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(122) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(121) D=top_0.data_encin1_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(67) D=top_0.data_encin1_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(67) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_60_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(66) D=top_0.data_encin1_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(66) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_61_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(65) D=top_0.data_encin1_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(65) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_62_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(64) D=top_0.data_encin1_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(64) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_63_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(63) D=top_0.data_encin1_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(63) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_64_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(62) D=top_0.data_encin1_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(62) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_65_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(61) D=top_0.data_encin1_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(61) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_66_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(60) D=top_0.data_encin1_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(60) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_67_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(59) D=top_0.data_encin1_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(59) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_68_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(58) D=top_0.data_encin1_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(58) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_69_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(121) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(120) D=top_0.data_encin1_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(57) D=top_0.data_encin1_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(57) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_70_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(56) D=top_0.data_encin1_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(56) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_71_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(55) D=top_0.data_encin1_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(55) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_72_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(54) D=top_0.data_encin1_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(54) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_73_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(53) D=top_0.data_encin1_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(53) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_74_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(52) D=top_0.data_encin1_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(52) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_75_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(51) D=top_0.data_encin1_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(51) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_76_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(50) D=top_0.data_encin1_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(50) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_77_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(49) D=top_0.data_encin1_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(49) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_78_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(48) D=top_0.data_encin1_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(48) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_79_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(120) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(119) D=top_0.data_encin1_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(47) D=top_0.data_encin1_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(47) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_80_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(46) D=top_0.data_encin1_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(46) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_81_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(45) D=top_0.data_encin1_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(45) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_82_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(44) D=top_0.data_encin1_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(44) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_83_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(43) D=top_0.data_encin1_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(43) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_84_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(42) D=top_0.data_encin1_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(42) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_85_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(41) D=top_0.data_encin1_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(41) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_86_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(40) D=top_0.data_encin1_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(40) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_87_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(39) D=top_0.data_encin1_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(39) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_88_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(38) D=top_0.data_encin1_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(38) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_89_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(119) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(118) D=top_0.data_encin1_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U011.datain(37) D=top_0.data_encin1_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(37) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_90_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(36) D=top_0.data_encin1_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(36) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_91_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(35) D=top_0.data_encin1_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(35) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_92_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(34) D=top_0.data_encin1_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(34) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_93_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(33) D=top_0.data_encin1_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(33) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_94_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(32) D=top_0.data_encin1_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(32) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_95_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(31) D=top_0.data_encin1_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(31) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_96_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(30) D=top_0.data_encin1_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(30) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_97_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(29) D=top_0.data_encin1_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(29) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_98_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U011.datain(28) D=top_0.data_encin1_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(28) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_99_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(118) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(127) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(127) D=top_0.data_encin_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(126) D=top_0.data_encin_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(117) D=top_0.data_encin_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(27) D=top_0.data_encin_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(27) I3=top_0.reset O=top_0.data_encin_ff_CQZ_100_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(26) D=top_0.data_encin_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(26) I3=top_0.reset O=top_0.data_encin_ff_CQZ_101_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(25) D=top_0.data_encin_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(25) I3=top_0.reset O=top_0.data_encin_ff_CQZ_102_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(24) D=top_0.data_encin_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(24) I3=top_0.reset O=top_0.data_encin_ff_CQZ_103_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(23) D=top_0.data_encin_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(23) I3=top_0.reset O=top_0.data_encin_ff_CQZ_104_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(22) D=top_0.data_encin_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(22) I3=top_0.reset O=top_0.data_encin_ff_CQZ_105_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(21) D=top_0.data_encin_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(21) I3=top_0.reset O=top_0.data_encin_ff_CQZ_106_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(20) D=top_0.data_encin_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(20) I3=top_0.reset O=top_0.data_encin_ff_CQZ_107_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(19) D=top_0.data_encin_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(19) I3=top_0.reset O=top_0.data_encin_ff_CQZ_108_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(18) D=top_0.data_encin_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(18) I3=top_0.reset O=top_0.data_encin_ff_CQZ_109_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(117) I3=top_0.reset O=top_0.data_encin_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(116) D=top_0.data_encin_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(17) D=top_0.data_encin_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(17) I3=top_0.reset O=top_0.data_encin_ff_CQZ_110_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(16) D=top_0.data_encin_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(16) I3=top_0.reset O=top_0.data_encin_ff_CQZ_111_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(15) D=top_0.data_encin_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(15) I3=top_0.reset O=top_0.data_encin_ff_CQZ_112_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(14) D=top_0.data_encin_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(14) I3=top_0.reset O=top_0.data_encin_ff_CQZ_113_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(13) D=top_0.data_encin_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(13) I3=top_0.reset O=top_0.data_encin_ff_CQZ_114_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(12) D=top_0.data_encin_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(12) I3=top_0.reset O=top_0.data_encin_ff_CQZ_115_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(11) D=top_0.data_encin_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(11) I3=top_0.reset O=top_0.data_encin_ff_CQZ_116_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(10) D=top_0.data_encin_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(10) I3=top_0.reset O=top_0.data_encin_ff_CQZ_117_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(9) D=top_0.data_encin_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(9) I3=top_0.reset O=top_0.data_encin_ff_CQZ_118_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(8) D=top_0.data_encin_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(8) I3=top_0.reset O=top_0.data_encin_ff_CQZ_119_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(116) I3=top_0.reset O=top_0.data_encin_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(115) D=top_0.data_encin_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(7) D=top_0.data_encin_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(7) I3=top_0.reset O=top_0.data_encin_ff_CQZ_120_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(6) D=top_0.data_encin_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(6) I3=top_0.reset O=top_0.data_encin_ff_CQZ_121_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(5) D=top_0.data_encin_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(5) I3=top_0.reset O=top_0.data_encin_ff_CQZ_122_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(4) D=top_0.data_encin_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(4) I3=top_0.reset O=top_0.data_encin_ff_CQZ_123_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(3) D=top_0.data_encin_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(3) I3=top_0.reset O=top_0.data_encin_ff_CQZ_124_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(2) D=top_0.data_encin_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(2) I3=top_0.reset O=top_0.data_encin_ff_CQZ_125_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(1) D=top_0.data_encin_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(1) I3=top_0.reset O=top_0.data_encin_ff_CQZ_126_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(0) D=top_0.data_encin_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(0) I3=top_0.reset O=top_0.data_encin_ff_CQZ_127_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(115) I3=top_0.reset O=top_0.data_encin_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(114) D=top_0.data_encin_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(114) I3=top_0.reset O=top_0.data_encin_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(113) D=top_0.data_encin_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(113) I3=top_0.reset O=top_0.data_encin_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(112) D=top_0.data_encin_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(112) I3=top_0.reset O=top_0.data_encin_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(111) D=top_0.data_encin_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(111) I3=top_0.reset O=top_0.data_encin_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(110) D=top_0.data_encin_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(110) I3=top_0.reset O=top_0.data_encin_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(109) D=top_0.data_encin_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(109) I3=top_0.reset O=top_0.data_encin_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(108) D=top_0.data_encin_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(108) I3=top_0.reset O=top_0.data_encin_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(126) I3=top_0.reset O=top_0.data_encin_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(125) D=top_0.data_encin_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(107) D=top_0.data_encin_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(107) I3=top_0.reset O=top_0.data_encin_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(106) D=top_0.data_encin_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(106) I3=top_0.reset O=top_0.data_encin_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(105) D=top_0.data_encin_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(105) I3=top_0.reset O=top_0.data_encin_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(104) D=top_0.data_encin_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(104) I3=top_0.reset O=top_0.data_encin_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(103) D=top_0.data_encin_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(103) I3=top_0.reset O=top_0.data_encin_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(102) D=top_0.data_encin_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(102) I3=top_0.reset O=top_0.data_encin_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(101) D=top_0.data_encin_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(101) I3=top_0.reset O=top_0.data_encin_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(100) D=top_0.data_encin_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(100) I3=top_0.reset O=top_0.data_encin_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(99) D=top_0.data_encin_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(99) I3=top_0.reset O=top_0.data_encin_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(98) D=top_0.data_encin_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(98) I3=top_0.reset O=top_0.data_encin_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(125) I3=top_0.reset O=top_0.data_encin_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(124) D=top_0.data_encin_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(97) D=top_0.data_encin_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(97) I3=top_0.reset O=top_0.data_encin_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(96) D=top_0.data_encin_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(96) I3=top_0.reset O=top_0.data_encin_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(95) D=top_0.data_encin_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(95) I3=top_0.reset O=top_0.data_encin_ff_CQZ_32_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(94) D=top_0.data_encin_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(94) I3=top_0.reset O=top_0.data_encin_ff_CQZ_33_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(93) D=top_0.data_encin_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(93) I3=top_0.reset O=top_0.data_encin_ff_CQZ_34_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(92) D=top_0.data_encin_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(92) I3=top_0.reset O=top_0.data_encin_ff_CQZ_35_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(91) D=top_0.data_encin_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(91) I3=top_0.reset O=top_0.data_encin_ff_CQZ_36_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(90) D=top_0.data_encin_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(90) I3=top_0.reset O=top_0.data_encin_ff_CQZ_37_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(89) D=top_0.data_encin_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(89) I3=top_0.reset O=top_0.data_encin_ff_CQZ_38_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(88) D=top_0.data_encin_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(88) I3=top_0.reset O=top_0.data_encin_ff_CQZ_39_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(124) I3=top_0.reset O=top_0.data_encin_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(123) D=top_0.data_encin_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(87) D=top_0.data_encin_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(87) I3=top_0.reset O=top_0.data_encin_ff_CQZ_40_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(86) D=top_0.data_encin_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(86) I3=top_0.reset O=top_0.data_encin_ff_CQZ_41_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(85) D=top_0.data_encin_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(85) I3=top_0.reset O=top_0.data_encin_ff_CQZ_42_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(84) D=top_0.data_encin_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(84) I3=top_0.reset O=top_0.data_encin_ff_CQZ_43_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(83) D=top_0.data_encin_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(83) I3=top_0.reset O=top_0.data_encin_ff_CQZ_44_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(82) D=top_0.data_encin_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(82) I3=top_0.reset O=top_0.data_encin_ff_CQZ_45_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(81) D=top_0.data_encin_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(81) I3=top_0.reset O=top_0.data_encin_ff_CQZ_46_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(80) D=top_0.data_encin_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(80) I3=top_0.reset O=top_0.data_encin_ff_CQZ_47_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(79) D=top_0.data_encin_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(79) I3=top_0.reset O=top_0.data_encin_ff_CQZ_48_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(78) D=top_0.data_encin_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(78) I3=top_0.reset O=top_0.data_encin_ff_CQZ_49_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(123) I3=top_0.reset O=top_0.data_encin_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(122) D=top_0.data_encin_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(77) D=top_0.data_encin_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(77) I3=top_0.reset O=top_0.data_encin_ff_CQZ_50_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(76) D=top_0.data_encin_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(76) I3=top_0.reset O=top_0.data_encin_ff_CQZ_51_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(75) D=top_0.data_encin_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(75) I3=top_0.reset O=top_0.data_encin_ff_CQZ_52_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(74) D=top_0.data_encin_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(74) I3=top_0.reset O=top_0.data_encin_ff_CQZ_53_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(73) D=top_0.data_encin_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(73) I3=top_0.reset O=top_0.data_encin_ff_CQZ_54_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(72) D=top_0.data_encin_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(72) I3=top_0.reset O=top_0.data_encin_ff_CQZ_55_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(71) D=top_0.data_encin_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(71) I3=top_0.reset O=top_0.data_encin_ff_CQZ_56_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(70) D=top_0.data_encin_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(70) I3=top_0.reset O=top_0.data_encin_ff_CQZ_57_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(69) D=top_0.data_encin_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(69) I3=top_0.reset O=top_0.data_encin_ff_CQZ_58_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(68) D=top_0.data_encin_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(68) I3=top_0.reset O=top_0.data_encin_ff_CQZ_59_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(122) I3=top_0.reset O=top_0.data_encin_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(121) D=top_0.data_encin_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(67) D=top_0.data_encin_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(67) I3=top_0.reset O=top_0.data_encin_ff_CQZ_60_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(66) D=top_0.data_encin_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(66) I3=top_0.reset O=top_0.data_encin_ff_CQZ_61_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(65) D=top_0.data_encin_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(65) I3=top_0.reset O=top_0.data_encin_ff_CQZ_62_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(64) D=top_0.data_encin_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(64) I3=top_0.reset O=top_0.data_encin_ff_CQZ_63_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(63) D=top_0.data_encin_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(63) I3=top_0.reset O=top_0.data_encin_ff_CQZ_64_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(62) D=top_0.data_encin_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(62) I3=top_0.reset O=top_0.data_encin_ff_CQZ_65_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(61) D=top_0.data_encin_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(61) I3=top_0.reset O=top_0.data_encin_ff_CQZ_66_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(60) D=top_0.data_encin_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(60) I3=top_0.reset O=top_0.data_encin_ff_CQZ_67_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(59) D=top_0.data_encin_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(59) I3=top_0.reset O=top_0.data_encin_ff_CQZ_68_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(58) D=top_0.data_encin_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(58) I3=top_0.reset O=top_0.data_encin_ff_CQZ_69_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(121) I3=top_0.reset O=top_0.data_encin_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(120) D=top_0.data_encin_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(57) D=top_0.data_encin_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(57) I3=top_0.reset O=top_0.data_encin_ff_CQZ_70_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(56) D=top_0.data_encin_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(56) I3=top_0.reset O=top_0.data_encin_ff_CQZ_71_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(55) D=top_0.data_encin_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(55) I3=top_0.reset O=top_0.data_encin_ff_CQZ_72_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(54) D=top_0.data_encin_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(54) I3=top_0.reset O=top_0.data_encin_ff_CQZ_73_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(53) D=top_0.data_encin_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(53) I3=top_0.reset O=top_0.data_encin_ff_CQZ_74_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(52) D=top_0.data_encin_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(52) I3=top_0.reset O=top_0.data_encin_ff_CQZ_75_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(51) D=top_0.data_encin_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(51) I3=top_0.reset O=top_0.data_encin_ff_CQZ_76_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(50) D=top_0.data_encin_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(50) I3=top_0.reset O=top_0.data_encin_ff_CQZ_77_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(49) D=top_0.data_encin_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(49) I3=top_0.reset O=top_0.data_encin_ff_CQZ_78_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(48) D=top_0.data_encin_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(48) I3=top_0.reset O=top_0.data_encin_ff_CQZ_79_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(120) I3=top_0.reset O=top_0.data_encin_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(119) D=top_0.data_encin_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(47) D=top_0.data_encin_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(47) I3=top_0.reset O=top_0.data_encin_ff_CQZ_80_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(46) D=top_0.data_encin_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(46) I3=top_0.reset O=top_0.data_encin_ff_CQZ_81_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(45) D=top_0.data_encin_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(45) I3=top_0.reset O=top_0.data_encin_ff_CQZ_82_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(44) D=top_0.data_encin_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(44) I3=top_0.reset O=top_0.data_encin_ff_CQZ_83_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(43) D=top_0.data_encin_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(43) I3=top_0.reset O=top_0.data_encin_ff_CQZ_84_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(42) D=top_0.data_encin_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(42) I3=top_0.reset O=top_0.data_encin_ff_CQZ_85_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(41) D=top_0.data_encin_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(41) I3=top_0.reset O=top_0.data_encin_ff_CQZ_86_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(40) D=top_0.data_encin_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(40) I3=top_0.reset O=top_0.data_encin_ff_CQZ_87_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(39) D=top_0.data_encin_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(39) I3=top_0.reset O=top_0.data_encin_ff_CQZ_88_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(38) D=top_0.data_encin_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(38) I3=top_0.reset O=top_0.data_encin_ff_CQZ_89_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(119) I3=top_0.reset O=top_0.data_encin_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(118) D=top_0.data_encin_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.U01.datain(37) D=top_0.data_encin_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(37) I3=top_0.reset O=top_0.data_encin_ff_CQZ_90_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(36) D=top_0.data_encin_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(36) I3=top_0.reset O=top_0.data_encin_ff_CQZ_91_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(35) D=top_0.data_encin_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(35) I3=top_0.reset O=top_0.data_encin_ff_CQZ_92_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(34) D=top_0.data_encin_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(34) I3=top_0.reset O=top_0.data_encin_ff_CQZ_93_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(33) D=top_0.data_encin_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(33) I3=top_0.reset O=top_0.data_encin_ff_CQZ_94_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(32) D=top_0.data_encin_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(32) I3=top_0.reset O=top_0.data_encin_ff_CQZ_95_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(31) D=top_0.data_encin_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(31) I3=top_0.reset O=top_0.data_encin_ff_CQZ_96_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(30) D=top_0.data_encin_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(30) I3=top_0.reset O=top_0.data_encin_ff_CQZ_97_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(29) D=top_0.data_encin_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(29) I3=top_0.reset O=top_0.data_encin_ff_CQZ_98_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.U01.datain(28) D=top_0.data_encin_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(28) I3=top_0.reset O=top_0.data_encin_ff_CQZ_99_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(118) I3=top_0.reset O=top_0.data_encin_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(127) I3=top_0.reset O=top_0.data_encin_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_0.data_encout1(6) D=top_0.data_encout1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout1(5) D=top_0.data_encout1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout1(4) D=top_0.data_encout1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout1(3) D=top_0.data_encout1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout1(2) D=top_0.data_encout1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout1(1) D=top_0.data_encout1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout1(0) D=top_0.data_encout1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3 O=top_0.data_encout1_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.reset I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(82) I1=top_0.U011.datain(81) I2=top_0.U011.datain(80) I3=top_0.U011.datain(83) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U011.datain(52) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(53) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(86) I1=top_0.reset I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(87) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(26) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(27) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.U011.datain(25) I3=top_0.U011.datain(24) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(30) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(31) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(30) I3=top_0.U011.datain(31) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.U011.datain(18) I2=top_0.U011.datain(17) I3=top_0.U011.datain(16) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.U011.datain(24) I2=top_0.U011.datain(26) I3=top_0.U011.datain(25) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(29) I3=top_0.U011.datain(28) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(91) I1=top_0.U011.datain(88) I2=top_0.U011.datain(90) I3=top_0.U011.datain(89) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.U011.datain(94) I2=top_0.U011.datain(93) I3=top_0.U011.datain(95) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3 O=top_0.data_encout1_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(73) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(72) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(74) I3=top_0.U011.datain(75) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(79) I1=top_0.U011.datain(78) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(76) I3=top_0.U011.datain(77) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000011111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(9) I1=top_0.U011.datain(8) I2=top_0.U011.datain(11) I3=top_0.U011.datain(10) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010100
|
|
.subckt LUT4 I0=top_0.U011.datain(12) I1=top_0.U011.datain(15) I2=top_0.U011.datain(14) I3=top_0.U011.datain(13) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(12) I3=top_0.U011.datain(13) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.U011.datain(29) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010111001111
|
|
.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.U011.datain(26) I2=top_0.U011.datain(25) I3=top_0.U011.datain(24) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(28) I1=top_0.U011.datain(29) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(30) I3=top_0.U011.datain(31) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(28) I1=top_0.U011.datain(31) I2=top_0.U011.datain(30) I3=top_0.U011.datain(29) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(45) I3=top_0.U011.datain(44) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(43) I1=top_0.U011.datain(40) I2=top_0.U011.datain(42) I3=top_0.U011.datain(41) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(46) I3=top_0.U011.datain(47) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(76) I1=top_0.U011.datain(79) I2=top_0.U011.datain(77) I3=top_0.U011.datain(78) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(75) I1=top_0.U011.datain(72) I2=top_0.U011.datain(74) I3=top_0.U011.datain(73) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(111) I3=top_0.U011.datain(110) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(109) I3=top_0.U011.datain(108) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(107) I1=top_0.U011.datain(104) I2=top_0.U011.datain(106) I3=top_0.U011.datain(105) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.U011.datain(102) I2=top_0.U011.datain(101) I3=top_0.U011.datain(100) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(110) I3=top_0.U011.datain(111) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(31) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(30) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.U011.datain(95) I2=top_0.U011.datain(93) I3=top_0.U011.datain(94) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(76) I1=top_0.U011.datain(78) I2=top_0.U011.datain(77) I3=top_0.U011.datain(79) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(74) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.U011.datain(75) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.U011.datain(75) I3=top_0.U011.datain(74) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(73) I3=top_0.U011.datain(72) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(76) I1=top_0.U011.datain(79) I2=top_0.U011.datain(78) I3=top_0.U011.datain(77) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.U011.datain(26) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(42) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(43) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(41) I3=top_0.U011.datain(40) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(106) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(107) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3 O=top_0.data_encout1_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(68) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(69) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.U011.datain(67) I1=top_0.U011.datain(66) I2=top_0.U011.datain(65) I3=top_0.U011.datain(64) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.U011.datain(6) I2=top_0.U011.datain(5) I3=top_0.U011.datain(4) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(21) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(20) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.U011.datain(22) I3=top_0.U011.datain(23) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D(6) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0 O=top_0.data_encout1_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.reset I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(18) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.U011.datain(6) I2=top_0.U011.datain(5) I3=top_0.U011.datain(4) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(3) I1=top_0.U011.datain(1) I2=top_0.U011.datain(0) I3=top_0.U011.datain(2) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(10) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(11) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(67) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(66) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(64) I3=top_0.U011.datain(65) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(87) I1=top_0.U011.datain(86) I2=top_0.U011.datain(85) I3=top_0.U011.datain(84) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(70) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(71) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(68) I3=top_0.U011.datain(69) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=top_0.U011.datain(86) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(87) I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(86) I3=top_0.U011.datain(87) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(84) I3=top_0.U011.datain(85) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(83) I1=top_0.U011.datain(82) I2=top_0.U011.datain(81) I3=top_0.U011.datain(80) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(23) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(22) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(23) I3=top_0.U011.datain(22) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.U011.datain(20) I3=top_0.U011.datain(21) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I3=top_0.U011.datain(6) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(14) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(15) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_0.data_encout1_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(89) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(88) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(93) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(92) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(93) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(94) I3=top_0.U011.datain(95) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(91) I3=top_0.U011.datain(90) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.U011.datain(89) I3=top_0.U011.datain(88) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(90) I3=top_0.U011.datain(91) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I2=top_0.reset I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(88) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(89) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(90) I3=top_0.U011.datain(91) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.U011.datain(95) I2=top_0.U011.datain(94) I3=top_0.U011.datain(93) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(83) I1=top_0.U011.datain(82) I2=top_0.U011.datain(81) I3=top_0.U011.datain(80) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111011101001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(84) I3=top_0.U011.datain(85) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(86) I3=top_0.U011.datain(87) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(98) I3=top_0.U011.datain(99) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(96) I3=top_0.U011.datain(97) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10011111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(109) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(108) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U011.datain(104) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(105) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.U011.datain(102) I2=top_0.U011.datain(101) I3=top_0.U011.datain(100) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(102) I3=top_0.U011.datain(103) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.reset I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(112) I3=top_0.U011.datain(113) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=top_0.U011.datain(117) I1=top_0.U011.datain(116) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_0.data_encout1_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(23) I1=top_0.U011.datain(22) I2=top_0.U011.datain(21) I3=top_0.U011.datain(20) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(16) I3=top_0.U011.datain(17) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(19) I3=top_0.U011.datain(18) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_0.U011.datain(10) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(11) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(8) I1=top_0.U011.datain(9) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(1) I1=top_0.U011.datain(0) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(3) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(71) I3=top_0.U011.datain(70) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(15) I3=top_0.U011.datain(14) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(12) I1=top_0.U011.datain(13) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(8) I1=top_0.U011.datain(11) I2=top_0.U011.datain(10) I3=top_0.U011.datain(9) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(6) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(7) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=top_0.U011.datain(4) I3=top_0.U011.datain(5) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.U011.datain(28) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.U011.datain(29) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.U011.datain(24) I2=top_0.U011.datain(26) I3=top_0.U011.datain(25) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(77) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.U011.datain(76) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.U011.datain(78) I3=top_0.U011.datain(79) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(73) I3=top_0.U011.datain(72) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.U011.datain(3) I1=top_0.U011.datain(2) I2=top_0.U011.datain(1) I3=top_0.U011.datain(0) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.U011.datain(6) I2=top_0.U011.datain(4) I3=top_0.U011.datain(5) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(12) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(13) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(14) I3=top_0.U011.datain(15) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(21) I3=top_0.U011.datain(20) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D(6) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(84) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(85) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.U011.datain(68) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(69) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(70) I3=top_0.U011.datain(71) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(64) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(65) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(64) I3=top_0.U011.datain(65) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(66) I3=top_0.U011.datain(67) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(71) I1=top_0.U011.datain(70) I2=top_0.U011.datain(69) I3=top_0.U011.datain(68) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(83) I1=top_0.U011.datain(82) I2=top_0.U011.datain(80) I3=top_0.U011.datain(81) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D(6) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(81) I1=top_0.U011.datain(80) I2=top_0.U011.datain(83) I3=top_0.U011.datain(82) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.U011.datain(18) I2=top_0.U011.datain(17) I3=top_0.U011.datain(16) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.U011.datain(18) I2=top_0.U011.datain(16) I3=top_0.U011.datain(17) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(8) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(9) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(10) I3=top_0.U011.datain(11) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(3) I1=top_0.U011.datain(0) I2=top_0.U011.datain(1) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=top_0.U011.datain(2) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(54) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(55) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.U011.datain(119) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(118) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(38) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(39) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.U011.datain(102) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(100) I3=top_0.U011.datain(101) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(99) I1=top_0.U011.datain(98) I2=top_0.U011.datain(97) I3=top_0.U011.datain(96) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(36) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(37) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(35) I1=top_0.U011.datain(33) I2=top_0.U011.datain(32) I3=top_0.U011.datain(34) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(99) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.U011.datain(98) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.U011.datain(48) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(49) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(48) I3=top_0.U011.datain(49) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(50) I3=top_0.U011.datain(51) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(55) I1=top_0.U011.datain(54) I2=top_0.U011.datain(53) I3=top_0.U011.datain(52) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(113) I3=top_0.U011.datain(112) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(114) I3=top_0.U011.datain(115) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(34) I3=top_0.U011.datain(35) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(33) I3=top_0.U011.datain(32) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.U011.datain(96) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(97) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(108) I1=top_0.U011.datain(111) I2=top_0.U011.datain(110) I3=top_0.U011.datain(109) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(98) I3=top_0.U011.datain(99) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(59) I1=top_0.U011.datain(56) I2=top_0.U011.datain(58) I3=top_0.U011.datain(57) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(50) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(51) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.U011.datain(43) I3=top_0.U011.datain(42) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(47) I3=top_0.U011.datain(46) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(125) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(124) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_0.U011.datain(58) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(59) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_0.U011.datain(58) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(62) I3=top_0.U011.datain(63) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(124) I1=top_0.U011.datain(127) I2=top_0.U011.datain(125) I3=top_0.U011.datain(126) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(38) I3=top_0.U011.datain(39) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.U011.datain(102) I2=top_0.U011.datain(100) I3=top_0.U011.datain(101) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(37) I3=top_0.U011.datain(36) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(38) I3=top_0.U011.datain(39) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(44) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(45) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(46) I3=top_0.U011.datain(47) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(56) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.U011.datain(57) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(61) I3=top_0.U011.datain(60) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U011.datain(59) I1=top_0.U011.datain(63) I2=top_0.U011.datain(62) I3=top_0.U011.datain(58) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(41) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(40) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(42) I3=top_0.U011.datain(43) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(44) I1=top_0.U011.datain(47) I2=top_0.U011.datain(46) I3=top_0.U011.datain(45) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U011.datain(50) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(51) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(48) I3=top_0.U011.datain(49) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(115) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(39) I3=top_0.U011.datain(38) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(36) I3=top_0.U011.datain(37) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(63) I3=top_0.U011.datain(62) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(124) I1=top_0.U011.datain(126) I2=top_0.U011.datain(125) I3=top_0.U011.datain(127) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(58) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(59) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(57) I3=top_0.U011.datain(56) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U011.datain(60) I1=top_0.U011.datain(63) I2=top_0.U011.datain(62) I3=top_0.U011.datain(61) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(50) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(51) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(55) I3=top_0.U011.datain(54) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(52) I3=top_0.U011.datain(53) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(118) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(119) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(107) I3=top_0.U011.datain(106) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(105) I3=top_0.U011.datain(104) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(119) I1=top_0.U011.datain(118) I2=top_0.U011.datain(117) I3=top_0.U011.datain(116) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(114) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.U011.datain(115) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.U011.datain(97) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(96) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(102) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(103) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(66) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(67) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(98) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(99) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(96) I3=top_0.U011.datain(97) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(32) I3=top_0.U011.datain(33) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(34) I1=top_0.U011.datain(33) I2=top_0.U011.datain(32) I3=top_0.U011.datain(35) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U011.datain(53) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.U011.datain(52) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(52) I3=top_0.U011.datain(53) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(54) I3=top_0.U011.datain(55) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(51) I1=top_0.U011.datain(50) I2=top_0.U011.datain(49) I3=top_0.U011.datain(48) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=top_0.U011.datain(116) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111111111
|
|
.subckt LUT4 I0=top_0.U011.datain(119) I1=top_0.U011.datain(118) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001111111111111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(116) I3=top_0.U011.datain(117) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U011.datain(116) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(117) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(115) I1=top_0.U011.datain(114) I2=top_0.U011.datain(113) I3=top_0.U011.datain(112) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(118) I3=top_0.U011.datain(119) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(61) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(60) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(61) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(60) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U011.datain(57) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(56) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(120) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(121) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(122) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.U011.datain(123) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(123) I3=top_0.U011.datain(122) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.U011.datain(121) I3=top_0.U011.datain(120) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(125) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(124) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(127) I3=top_0.U011.datain(126) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(123) I1=top_0.U011.datain(120) I2=top_0.U011.datain(122) I3=top_0.U011.datain(121) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(121) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(120) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(122) I3=top_0.U011.datain(123) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U011.datain(124) I1=top_0.U011.datain(126) I2=top_0.U011.datain(127) I3=top_0.U011.datain(125) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(109) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(108) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(110) I3=top_0.U011.datain(111) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U011.datain(105) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(104) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(106) I3=top_0.U011.datain(107) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U011.datain(41) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.U011.datain(40) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U011.datain(45) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(44) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U011.datain(35) I1=top_0.U011.datain(34) I2=top_0.U011.datain(33) I3=top_0.U011.datain(32) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U011.datain(39) I1=top_0.U011.datain(38) I2=top_0.U011.datain(37) I3=top_0.U011.datain(36) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=top_0.U011.datain(115) I1=top_0.U011.datain(114) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(112) I3=top_0.U011.datain(113) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(48) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=top_0.data_encout(6) D=top_0.data_encout_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout(5) D=top_0.data_encout_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout(4) D=top_0.data_encout_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout(3) D=top_0.data_encout_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout(2) D=top_0.data_encout_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout(1) D=top_0.data_encout_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_0.data_encout(0) D=top_0.data_encout_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3 O=top_0.data_encout_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(75) I3=top_0.U01.datain(74) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.U01.datain(71) I1=top_0.U01.datain(70) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(68) I3=top_0.U01.datain(69) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(77) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(76) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(79) I3=top_0.U01.datain(78) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.U01.datain(14) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U01.datain(15) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(13) I3=top_0.U01.datain(12) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111111111
|
|
.subckt LUT4 I0=top_0.U01.datain(12) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U01.datain(13) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(15) I3=top_0.U01.datain(14) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=top_0.U01.datain(9) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(8) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(10) I3=top_0.U01.datain(11) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U01.datain(13) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=top_0.U01.datain(12) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(8) I1=top_0.U01.datain(10) I2=top_0.U01.datain(9) I3=top_0.U01.datain(11) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(11) I1=top_0.U01.datain(8) I2=top_0.U01.datain(9) I3=top_0.U01.datain(10) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(9) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.U01.datain(8) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3 O=top_0.data_encout_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2 I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(125) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.U01.datain(124) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(61) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.U01.datain(60) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(63) I3=top_0.U01.datain(62) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U01.datain(4) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3 I2=top_0.U01.datain(5) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(18) I3=top_0.U01.datain(19) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I2=top_0.U01.datain(16) I3=top_0.U01.datain(17) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.U01.datain(18) I2=top_0.U01.datain(17) I3=top_0.U01.datain(16) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.U01.datain(18) I2=top_0.U01.datain(17) I3=top_0.U01.datain(16) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(23) I1=top_0.U01.datain(22) I2=top_0.U01.datain(21) I3=top_0.U01.datain(20) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010110
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(28) I1=top_0.U01.datain(31) I2=top_0.U01.datain(30) I3=top_0.U01.datain(29) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(27) I1=top_0.U01.datain(24) I2=top_0.U01.datain(26) I3=top_0.U01.datain(25) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I1=top_0.U01.datain(4) I2=top_0.U01.datain(5) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001110000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(7) I1=top_0.U01.datain(6) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(3) I1=top_0.U01.datain(2) I2=top_0.U01.datain(1) I3=top_0.U01.datain(0) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3 O=top_0.data_encout_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.U01.datain(99) I3=top_0.U01.datain(98) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(35) I3=top_0.U01.datain(34) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(96) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(97) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(96) I3=top_0.U01.datain(97) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(98) I3=top_0.U01.datain(99) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.U01.datain(101) I3=top_0.U01.datain(100) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(34) I2=top_0.U01.datain(35) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.U01.datain(32) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(33) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(33) I1=top_0.U01.datain(32) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(34) I3=top_0.U01.datain(35) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.U01.datain(37) I3=top_0.U01.datain(36) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(33) I1=top_0.U01.datain(32) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(37) I1=top_0.U01.datain(36) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(43) I1=top_0.U01.datain(40) I2=top_0.U01.datain(42) I3=top_0.U01.datain(41) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(41) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.U01.datain(107) I2=top_0.U01.datain(106) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=top_0.U01.datain(106) I3=top_0.U01.datain(107) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10011111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(105) I3=top_0.U01.datain(104) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(96) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(115) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.U01.datain(114) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(114) I3=top_0.U01.datain(115) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(113) I3=top_0.U01.datain(112) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(119) I1=top_0.U01.datain(118) I2=top_0.U01.datain(116) I3=top_0.U01.datain(117) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(49) I3=top_0.U01.datain(48) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(50) I3=top_0.U01.datain(51) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.U01.datain(44) I1=top_0.U01.datain(47) I2=top_0.U01.datain(46) I3=top_0.U01.datain(45) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(40) I1=top_0.U01.datain(43) I2=top_0.U01.datain(42) I3=top_0.U01.datain(41) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(45) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(44) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(46) I3=top_0.U01.datain(47) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U01.datain(41) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(40) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(42) I3=top_0.U01.datain(43) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(104) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(105) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(109) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(108) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(111) I3=top_0.U01.datain(110) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U01.datain(107) I1=top_0.U01.datain(104) I2=top_0.U01.datain(106) I3=top_0.U01.datain(105) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(105) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(104) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(106) I3=top_0.U01.datain(107) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U01.datain(108) I1=top_0.U01.datain(110) I2=top_0.U01.datain(109) I3=top_0.U01.datain(111) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I1=top_0.U01.datain(107) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(43) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(121) I1=top_0.U01.datain(125) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111101011001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(127) I3=top_0.U01.datain(126) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(121) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=top_0.U01.datain(120) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.U01.datain(122) I3=top_0.U01.datain(123) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(59) I1=top_0.U01.datain(62) I2=top_0.U01.datain(60) I3=top_0.U01.datain(56) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_0.U01.datain(61) I1=top_0.U01.datain(63) I2=top_0.U01.datain(58) I3=top_0.U01.datain(57) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(123) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.U01.datain(122) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(59) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(58) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3 O=top_0.data_encout_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(51) I1=top_0.U01.datain(50) I2=top_0.U01.datain(49) I3=top_0.U01.datain(48) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.U01.datain(35) I2=top_0.U01.datain(34) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=top_0.U01.datain(47) I2=top_0.U01.datain(46) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(69) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0 I3=top_0.U01.datain(68) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(100) I3=top_0.U01.datain(101) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.U01.datain(101) I3=top_0.U01.datain(100) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_0.U01.datain(39) I2=top_0.U01.datain(38) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(95) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.U01.datain(94) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(31) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U01.datain(30) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(30) I3=top_0.U01.datain(31) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(29) I3=top_0.U01.datain(28) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(127) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(126) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(123) I1=top_0.U01.datain(120) I2=top_0.U01.datain(121) I3=top_0.U01.datain(122) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(125) I3=top_0.U01.datain(124) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(60) I1=top_0.U01.datain(61) I2=top_0.U01.datain(63) I3=top_0.U01.datain(62) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.U01.datain(59) I1=top_0.U01.datain(56) I2=top_0.U01.datain(58) I3=top_0.U01.datain(57) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.U01.datain(47) I1=top_0.U01.datain(46) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(45) I3=top_0.U01.datain(44) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(109) I3=top_0.U01.datain(108) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(110) I3=top_0.U01.datain(111) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(76) I1=top_0.U01.datain(77) I2=top_0.U01.datain(79) I3=top_0.U01.datain(78) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(68) I3=top_0.U01.datain(69) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(67) I1=top_0.U01.datain(66) I2=top_0.U01.datain(65) I3=top_0.U01.datain(64) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(70) I3=top_0.U01.datain(71) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.U01.datain(119) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(118) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(115) I1=top_0.U01.datain(114) I2=top_0.U01.datain(112) I3=top_0.U01.datain(113) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(118) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(119) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(117) I3=top_0.U01.datain(116) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(52) I3=top_0.U01.datain(53) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U01.datain(51) I1=top_0.U01.datain(50) I2=top_0.U01.datain(48) I3=top_0.U01.datain(49) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(54) I3=top_0.U01.datain(55) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(15) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(14) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.U01.datain(102) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(7) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.U01.datain(6) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(5) I1=top_0.U01.datain(4) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_0.U01.datain(20) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(23) I1=top_0.U01.datain(22) I2=top_0.U01.datain(21) I3=top_0.U01.datain(20) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(82) I2=top_0.U01.datain(80) I3=top_0.U01.datain(81) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(86) I2=top_0.U01.datain(85) I3=top_0.U01.datain(84) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(117) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(116) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(55) I1=top_0.U01.datain(54) I2=top_0.U01.datain(53) I3=top_0.U01.datain(52) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3 O=top_0.data_encout_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(66) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(67) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(98) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.U01.datain(99) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(96) I3=top_0.U01.datain(97) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(34) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.U01.datain(35) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I1=top_0.U01.datain(2) I2=top_0.U01.datain(3) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001110000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O I3=top_0.U01.datain(18) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(74) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(75) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(73) I3=top_0.U01.datain(72) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.U01.datain(42) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(106) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111101110111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3 O=top_0.data_encout_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(71) I3=top_0.U01.datain(70) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.U01.datain(46) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.U01.datain(47) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(76) I1=top_0.U01.datain(78) I2=top_0.U01.datain(77) I3=top_0.U01.datain(79) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.U01.datain(6) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(7) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.U01.datain(38) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=top_0.U01.datain(39) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U01.datain(102) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.U01.datain(103) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(68) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(69) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(77) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U01.datain(76) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(109) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.U01.datain(108) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(45) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U01.datain(44) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.U01.datain(100) I3=top_0.U01.datain(101) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(99) I1=top_0.U01.datain(98) I2=top_0.U01.datain(97) I3=top_0.U01.datain(96) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.U01.datain(36) I3=top_0.U01.datain(37) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(35) I1=top_0.U01.datain(34) I2=top_0.U01.datain(33) I3=top_0.U01.datain(32) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.U01.datain(37) I3=top_0.U01.datain(36) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(67) I3=top_0.U01.datain(66) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(2) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(3) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(1) I1=top_0.U01.datain(0) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=top_0.U01.datain(18) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(19) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100000001111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(64) I3=top_0.U01.datain(65) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(75) I1=top_0.U01.datain(72) I2=top_0.U01.datain(74) I3=top_0.U01.datain(73) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(76) I1=top_0.U01.datain(78) I2=top_0.U01.datain(77) I3=top_0.U01.datain(79) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(64) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(65) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(65) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(64) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(66) I3=top_0.U01.datain(67) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U01.datain(71) I1=top_0.U01.datain(70) I2=top_0.U01.datain(69) I3=top_0.U01.datain(68) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.U01.datain(18) I2=top_0.U01.datain(16) I3=top_0.U01.datain(17) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(11) I1=top_0.U01.datain(8) I2=top_0.U01.datain(10) I3=top_0.U01.datain(9) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(12) I1=top_0.U01.datain(14) I2=top_0.U01.datain(13) I3=top_0.U01.datain(15) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(7) I1=top_0.U01.datain(6) I2=top_0.U01.datain(5) I3=top_0.U01.datain(4) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(3) I1=top_0.U01.datain(2) I2=top_0.U01.datain(0) I3=top_0.U01.datain(1) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=top_0.U01.datain(72) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U01.datain(73) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(73) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(72) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(74) I3=top_0.U01.datain(75) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101000000
|
|
.subckt LUT4 I0=top_0.U01.datain(95) I1=top_0.U01.datain(94) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(93) I3=top_0.U01.datain(92) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(91) I1=top_0.U01.datain(88) I2=top_0.U01.datain(89) I3=top_0.U01.datain(90) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000111111111
|
|
.subckt LUT4 I0=top_0.U01.datain(92) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.U01.datain(93) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(94) I3=top_0.U01.datain(95) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.U01.datain(91) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(90) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(89) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(88) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U01.datain(93) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(92) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(82) I2=top_0.U01.datain(80) I3=top_0.U01.datain(81) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(82) I2=top_0.U01.datain(80) I3=top_0.U01.datain(81) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(122) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(123) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(121) I3=top_0.U01.datain(120) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(124) I1=top_0.U01.datain(125) I2=top_0.U01.datain(126) I3=top_0.U01.datain(127) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(58) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(59) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(57) I3=top_0.U01.datain(56) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(60) I1=top_0.U01.datain(62) I2=top_0.U01.datain(61) I3=top_0.U01.datain(63) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(114) I3=top_0.U01.datain(115) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(113) I3=top_0.U01.datain(112) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(51) I1=top_0.U01.datain(50) I2=top_0.U01.datain(48) I3=top_0.U01.datain(49) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(55) I1=top_0.U01.datain(54) I2=top_0.U01.datain(53) I3=top_0.U01.datain(52) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(113) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(112) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(113) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(112) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(111) I3=top_0.U01.datain(110) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(29) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(28) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(30) I3=top_0.U01.datain(31) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(116) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(117) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(118) I3=top_0.U01.datain(119) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(55) I1=top_0.U01.datain(54) I2=top_0.U01.datain(52) I3=top_0.U01.datain(53) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(86) I2=top_0.U01.datain(84) I3=top_0.U01.datain(85) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(23) I1=top_0.U01.datain(22) I2=top_0.U01.datain(20) I3=top_0.U01.datain(21) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.U01.datain(60) I1=top_0.U01.datain(62) I2=top_0.U01.datain(61) I3=top_0.U01.datain(63) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(55) I3=top_0.U01.datain(54) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(94) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.U01.datain(95) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(30) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(31) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(86) I1=top_0.U01.datain(84) I2=top_0.U01.datain(85) I3=top_0.U01.datain(87) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(22) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(23) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(20) I3=top_0.U01.datain(21) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.U01.datain(29) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(28) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_0.U01.datain(25) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(24) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(26) I3=top_0.U01.datain(27) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=top_0.U01.datain(126) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.U01.datain(127) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(56) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(57) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(58) I3=top_0.U01.datain(59) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(89) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U01.datain(88) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(90) I3=top_0.U01.datain(91) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(26) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.U01.datain(27) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(27) I1=top_0.U01.datain(24) I2=top_0.U01.datain(26) I3=top_0.U01.datain(25) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(82) I1=top_0.U01.datain(80) I2=top_0.U01.datain(81) I3=top_0.U01.datain(83) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.U01.datain(114) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(115) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(51) I3=top_0.U01.datain(50) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(86) I2=top_0.U01.datain(84) I3=top_0.U01.datain(85) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(80) I2=top_0.U01.datain(81) I3=top_0.U01.datain(82) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.U01.datain(90) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(91) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(89) I3=top_0.U01.datain(88) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(92) I1=top_0.U01.datain(95) I2=top_0.U01.datain(94) I3=top_0.U01.datain(93) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(27) I3=top_0.U01.datain(26) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(25) I3=top_0.U01.datain(24) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=top_0.U01.datain(22) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(84) I2=top_0.U01.datain(85) I3=top_0.U01.datain(86) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt ff CQZ=top_1.U011.datain(127) D=top_1.data_encin1_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(126) D=top_1.data_encin1_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(117) D=top_1.data_encin1_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(27) D=top_1.data_encin1_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(27) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_100_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(26) D=top_1.data_encin1_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(26) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_101_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(25) D=top_1.data_encin1_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(25) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_102_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(24) D=top_1.data_encin1_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(24) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_103_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(23) D=top_1.data_encin1_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(23) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_104_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(22) D=top_1.data_encin1_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(22) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_105_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(21) D=top_1.data_encin1_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(21) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_106_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(20) D=top_1.data_encin1_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(20) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_107_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(19) D=top_1.data_encin1_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(19) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_108_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(18) D=top_1.data_encin1_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(18) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_109_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(117) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(116) D=top_1.data_encin1_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(17) D=top_1.data_encin1_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(17) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_110_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(16) D=top_1.data_encin1_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(16) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_111_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(15) D=top_1.data_encin1_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(15) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_112_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(14) D=top_1.data_encin1_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(14) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_113_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(13) D=top_1.data_encin1_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(13) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_114_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(12) D=top_1.data_encin1_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(12) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_115_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(11) D=top_1.data_encin1_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(11) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_116_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(10) D=top_1.data_encin1_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(10) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_117_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(9) D=top_1.data_encin1_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(9) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_118_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(8) D=top_1.data_encin1_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(8) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_119_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(116) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(115) D=top_1.data_encin1_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(7) D=top_1.data_encin1_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(7) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_120_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(6) D=top_1.data_encin1_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(6) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_121_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(5) D=top_1.data_encin1_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(5) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_122_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(4) D=top_1.data_encin1_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(4) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_123_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(3) D=top_1.data_encin1_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(3) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_124_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(2) D=top_1.data_encin1_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(2) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_125_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(1) D=top_1.data_encin1_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(1) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_126_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(0) D=top_1.data_encin1_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(0) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_127_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(115) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(114) D=top_1.data_encin1_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(114) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(113) D=top_1.data_encin1_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(113) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(112) D=top_1.data_encin1_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(112) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(111) D=top_1.data_encin1_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(111) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(110) D=top_1.data_encin1_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(110) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(109) D=top_1.data_encin1_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(109) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(108) D=top_1.data_encin1_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(108) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(126) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(125) D=top_1.data_encin1_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(107) D=top_1.data_encin1_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(107) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(106) D=top_1.data_encin1_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(106) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(105) D=top_1.data_encin1_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(105) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(104) D=top_1.data_encin1_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(104) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(103) D=top_1.data_encin1_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(103) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(102) D=top_1.data_encin1_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(102) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(101) D=top_1.data_encin1_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(101) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(100) D=top_1.data_encin1_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(100) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(99) D=top_1.data_encin1_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(99) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(98) D=top_1.data_encin1_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(98) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(125) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(124) D=top_1.data_encin1_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(97) D=top_1.data_encin1_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(97) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(96) D=top_1.data_encin1_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(96) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(95) D=top_1.data_encin1_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(95) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_32_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(94) D=top_1.data_encin1_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(94) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_33_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(93) D=top_1.data_encin1_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(93) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_34_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(92) D=top_1.data_encin1_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(92) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_35_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(91) D=top_1.data_encin1_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(91) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_36_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(90) D=top_1.data_encin1_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(90) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_37_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(89) D=top_1.data_encin1_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(89) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_38_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(88) D=top_1.data_encin1_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(88) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_39_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(124) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(123) D=top_1.data_encin1_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(87) D=top_1.data_encin1_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(87) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_40_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(86) D=top_1.data_encin1_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(86) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_41_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(85) D=top_1.data_encin1_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(85) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_42_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(84) D=top_1.data_encin1_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(84) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_43_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(83) D=top_1.data_encin1_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(83) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_44_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(82) D=top_1.data_encin1_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(82) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_45_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(81) D=top_1.data_encin1_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(81) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_46_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(80) D=top_1.data_encin1_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(80) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_47_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(79) D=top_1.data_encin1_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(79) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_48_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(78) D=top_1.data_encin1_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(78) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_49_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(123) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(122) D=top_1.data_encin1_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(77) D=top_1.data_encin1_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(77) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_50_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(76) D=top_1.data_encin1_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(76) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_51_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(75) D=top_1.data_encin1_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(75) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_52_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(74) D=top_1.data_encin1_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(74) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_53_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(73) D=top_1.data_encin1_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(73) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_54_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(72) D=top_1.data_encin1_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(72) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_55_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(71) D=top_1.data_encin1_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(71) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_56_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(70) D=top_1.data_encin1_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(70) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_57_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(69) D=top_1.data_encin1_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(69) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_58_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(68) D=top_1.data_encin1_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(68) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_59_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(122) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(121) D=top_1.data_encin1_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(67) D=top_1.data_encin1_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(67) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_60_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(66) D=top_1.data_encin1_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(66) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_61_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(65) D=top_1.data_encin1_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(65) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_62_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(64) D=top_1.data_encin1_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(64) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_63_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(63) D=top_1.data_encin1_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(63) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_64_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(62) D=top_1.data_encin1_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(62) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_65_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(61) D=top_1.data_encin1_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(61) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_66_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(60) D=top_1.data_encin1_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(60) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_67_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(59) D=top_1.data_encin1_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(59) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_68_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(58) D=top_1.data_encin1_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(58) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_69_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(121) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(120) D=top_1.data_encin1_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(57) D=top_1.data_encin1_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(57) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_70_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(56) D=top_1.data_encin1_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(56) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_71_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(55) D=top_1.data_encin1_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(55) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_72_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(54) D=top_1.data_encin1_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(54) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_73_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(53) D=top_1.data_encin1_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(53) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_74_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(52) D=top_1.data_encin1_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(52) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_75_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(51) D=top_1.data_encin1_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(51) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_76_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(50) D=top_1.data_encin1_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(50) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_77_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(49) D=top_1.data_encin1_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(49) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_78_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(48) D=top_1.data_encin1_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(48) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_79_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(120) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(119) D=top_1.data_encin1_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(47) D=top_1.data_encin1_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(47) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_80_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(46) D=top_1.data_encin1_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(46) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_81_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(45) D=top_1.data_encin1_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(45) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_82_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(44) D=top_1.data_encin1_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(44) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_83_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(43) D=top_1.data_encin1_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(43) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_84_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(42) D=top_1.data_encin1_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(42) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_85_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(41) D=top_1.data_encin1_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(41) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_86_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(40) D=top_1.data_encin1_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(40) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_87_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(39) D=top_1.data_encin1_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(39) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_88_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(38) D=top_1.data_encin1_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(38) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_89_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(119) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(118) D=top_1.data_encin1_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U011.datain(37) D=top_1.data_encin1_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(37) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_90_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(36) D=top_1.data_encin1_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(36) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_91_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(35) D=top_1.data_encin1_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(35) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_92_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(34) D=top_1.data_encin1_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(34) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_93_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(33) D=top_1.data_encin1_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(33) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_94_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(32) D=top_1.data_encin1_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(32) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_95_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(31) D=top_1.data_encin1_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(31) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_96_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(30) D=top_1.data_encin1_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(30) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_97_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(29) D=top_1.data_encin1_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(29) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_98_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U011.datain(28) D=top_1.data_encin1_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(28) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_99_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(118) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(127) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(127) D=top_1.data_encin_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(126) D=top_1.data_encin_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(117) D=top_1.data_encin_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(27) D=top_1.data_encin_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(27) I3=top_0.reset O=top_1.data_encin_ff_CQZ_100_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(26) D=top_1.data_encin_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(26) I3=top_0.reset O=top_1.data_encin_ff_CQZ_101_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(25) D=top_1.data_encin_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(25) I3=top_0.reset O=top_1.data_encin_ff_CQZ_102_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(24) D=top_1.data_encin_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(24) I3=top_0.reset O=top_1.data_encin_ff_CQZ_103_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(23) D=top_1.data_encin_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(23) I3=top_0.reset O=top_1.data_encin_ff_CQZ_104_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(22) D=top_1.data_encin_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(22) I3=top_0.reset O=top_1.data_encin_ff_CQZ_105_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(21) D=top_1.data_encin_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(21) I3=top_0.reset O=top_1.data_encin_ff_CQZ_106_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(20) D=top_1.data_encin_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(20) I3=top_0.reset O=top_1.data_encin_ff_CQZ_107_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(19) D=top_1.data_encin_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(19) I3=top_0.reset O=top_1.data_encin_ff_CQZ_108_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(18) D=top_1.data_encin_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(18) I3=top_0.reset O=top_1.data_encin_ff_CQZ_109_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(117) I3=top_0.reset O=top_1.data_encin_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(116) D=top_1.data_encin_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(17) D=top_1.data_encin_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(17) I3=top_0.reset O=top_1.data_encin_ff_CQZ_110_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(16) D=top_1.data_encin_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(16) I3=top_0.reset O=top_1.data_encin_ff_CQZ_111_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(15) D=top_1.data_encin_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(15) I3=top_0.reset O=top_1.data_encin_ff_CQZ_112_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(14) D=top_1.data_encin_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(14) I3=top_0.reset O=top_1.data_encin_ff_CQZ_113_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(13) D=top_1.data_encin_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(13) I3=top_0.reset O=top_1.data_encin_ff_CQZ_114_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(12) D=top_1.data_encin_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(12) I3=top_0.reset O=top_1.data_encin_ff_CQZ_115_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(11) D=top_1.data_encin_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(11) I3=top_0.reset O=top_1.data_encin_ff_CQZ_116_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(10) D=top_1.data_encin_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(10) I3=top_0.reset O=top_1.data_encin_ff_CQZ_117_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(9) D=top_1.data_encin_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(9) I3=top_0.reset O=top_1.data_encin_ff_CQZ_118_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(8) D=top_1.data_encin_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(8) I3=top_0.reset O=top_1.data_encin_ff_CQZ_119_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(116) I3=top_0.reset O=top_1.data_encin_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(115) D=top_1.data_encin_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(7) D=top_1.data_encin_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(7) I3=top_0.reset O=top_1.data_encin_ff_CQZ_120_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(6) D=top_1.data_encin_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(6) I3=top_0.reset O=top_1.data_encin_ff_CQZ_121_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(5) D=top_1.data_encin_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(5) I3=top_0.reset O=top_1.data_encin_ff_CQZ_122_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(4) D=top_1.data_encin_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(4) I3=top_0.reset O=top_1.data_encin_ff_CQZ_123_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(3) D=top_1.data_encin_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(3) I3=top_0.reset O=top_1.data_encin_ff_CQZ_124_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(2) D=top_1.data_encin_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(2) I3=top_0.reset O=top_1.data_encin_ff_CQZ_125_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(1) D=top_1.data_encin_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(1) I3=top_0.reset O=top_1.data_encin_ff_CQZ_126_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(0) D=top_1.data_encin_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(0) I3=top_0.reset O=top_1.data_encin_ff_CQZ_127_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(115) I3=top_0.reset O=top_1.data_encin_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(114) D=top_1.data_encin_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(114) I3=top_0.reset O=top_1.data_encin_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(113) D=top_1.data_encin_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(113) I3=top_0.reset O=top_1.data_encin_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(112) D=top_1.data_encin_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(112) I3=top_0.reset O=top_1.data_encin_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(111) D=top_1.data_encin_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(111) I3=top_0.reset O=top_1.data_encin_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(110) D=top_1.data_encin_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(110) I3=top_0.reset O=top_1.data_encin_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(109) D=top_1.data_encin_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(109) I3=top_0.reset O=top_1.data_encin_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(108) D=top_1.data_encin_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(108) I3=top_0.reset O=top_1.data_encin_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(126) I3=top_0.reset O=top_1.data_encin_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(125) D=top_1.data_encin_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(107) D=top_1.data_encin_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(107) I3=top_0.reset O=top_1.data_encin_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(106) D=top_1.data_encin_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(106) I3=top_0.reset O=top_1.data_encin_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(105) D=top_1.data_encin_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(105) I3=top_0.reset O=top_1.data_encin_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(104) D=top_1.data_encin_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(104) I3=top_0.reset O=top_1.data_encin_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(103) D=top_1.data_encin_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(103) I3=top_0.reset O=top_1.data_encin_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(102) D=top_1.data_encin_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(102) I3=top_0.reset O=top_1.data_encin_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(101) D=top_1.data_encin_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(101) I3=top_0.reset O=top_1.data_encin_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(100) D=top_1.data_encin_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(100) I3=top_0.reset O=top_1.data_encin_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(99) D=top_1.data_encin_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(99) I3=top_0.reset O=top_1.data_encin_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(98) D=top_1.data_encin_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(98) I3=top_0.reset O=top_1.data_encin_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(125) I3=top_0.reset O=top_1.data_encin_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(124) D=top_1.data_encin_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(97) D=top_1.data_encin_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(97) I3=top_0.reset O=top_1.data_encin_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(96) D=top_1.data_encin_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(96) I3=top_0.reset O=top_1.data_encin_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(95) D=top_1.data_encin_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(95) I3=top_0.reset O=top_1.data_encin_ff_CQZ_32_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(94) D=top_1.data_encin_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(94) I3=top_0.reset O=top_1.data_encin_ff_CQZ_33_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(93) D=top_1.data_encin_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(93) I3=top_0.reset O=top_1.data_encin_ff_CQZ_34_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(92) D=top_1.data_encin_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(92) I3=top_0.reset O=top_1.data_encin_ff_CQZ_35_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(91) D=top_1.data_encin_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(91) I3=top_0.reset O=top_1.data_encin_ff_CQZ_36_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(90) D=top_1.data_encin_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(90) I3=top_0.reset O=top_1.data_encin_ff_CQZ_37_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(89) D=top_1.data_encin_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(89) I3=top_0.reset O=top_1.data_encin_ff_CQZ_38_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(88) D=top_1.data_encin_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(88) I3=top_0.reset O=top_1.data_encin_ff_CQZ_39_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(124) I3=top_0.reset O=top_1.data_encin_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(123) D=top_1.data_encin_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(87) D=top_1.data_encin_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(87) I3=top_0.reset O=top_1.data_encin_ff_CQZ_40_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(86) D=top_1.data_encin_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(86) I3=top_0.reset O=top_1.data_encin_ff_CQZ_41_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(85) D=top_1.data_encin_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(85) I3=top_0.reset O=top_1.data_encin_ff_CQZ_42_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(84) D=top_1.data_encin_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(84) I3=top_0.reset O=top_1.data_encin_ff_CQZ_43_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(83) D=top_1.data_encin_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(83) I3=top_0.reset O=top_1.data_encin_ff_CQZ_44_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(82) D=top_1.data_encin_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(82) I3=top_0.reset O=top_1.data_encin_ff_CQZ_45_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(81) D=top_1.data_encin_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(81) I3=top_0.reset O=top_1.data_encin_ff_CQZ_46_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(80) D=top_1.data_encin_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(80) I3=top_0.reset O=top_1.data_encin_ff_CQZ_47_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(79) D=top_1.data_encin_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(79) I3=top_0.reset O=top_1.data_encin_ff_CQZ_48_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(78) D=top_1.data_encin_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(78) I3=top_0.reset O=top_1.data_encin_ff_CQZ_49_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(123) I3=top_0.reset O=top_1.data_encin_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(122) D=top_1.data_encin_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(77) D=top_1.data_encin_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(77) I3=top_0.reset O=top_1.data_encin_ff_CQZ_50_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(76) D=top_1.data_encin_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(76) I3=top_0.reset O=top_1.data_encin_ff_CQZ_51_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(75) D=top_1.data_encin_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(75) I3=top_0.reset O=top_1.data_encin_ff_CQZ_52_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(74) D=top_1.data_encin_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(74) I3=top_0.reset O=top_1.data_encin_ff_CQZ_53_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(73) D=top_1.data_encin_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(73) I3=top_0.reset O=top_1.data_encin_ff_CQZ_54_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(72) D=top_1.data_encin_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(72) I3=top_0.reset O=top_1.data_encin_ff_CQZ_55_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(71) D=top_1.data_encin_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(71) I3=top_0.reset O=top_1.data_encin_ff_CQZ_56_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(70) D=top_1.data_encin_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(70) I3=top_0.reset O=top_1.data_encin_ff_CQZ_57_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(69) D=top_1.data_encin_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(69) I3=top_0.reset O=top_1.data_encin_ff_CQZ_58_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(68) D=top_1.data_encin_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(68) I3=top_0.reset O=top_1.data_encin_ff_CQZ_59_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(122) I3=top_0.reset O=top_1.data_encin_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(121) D=top_1.data_encin_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(67) D=top_1.data_encin_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(67) I3=top_0.reset O=top_1.data_encin_ff_CQZ_60_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(66) D=top_1.data_encin_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(66) I3=top_0.reset O=top_1.data_encin_ff_CQZ_61_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(65) D=top_1.data_encin_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(65) I3=top_0.reset O=top_1.data_encin_ff_CQZ_62_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(64) D=top_1.data_encin_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(64) I3=top_0.reset O=top_1.data_encin_ff_CQZ_63_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(63) D=top_1.data_encin_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(63) I3=top_0.reset O=top_1.data_encin_ff_CQZ_64_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(62) D=top_1.data_encin_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(62) I3=top_0.reset O=top_1.data_encin_ff_CQZ_65_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(61) D=top_1.data_encin_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(61) I3=top_0.reset O=top_1.data_encin_ff_CQZ_66_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(60) D=top_1.data_encin_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(60) I3=top_0.reset O=top_1.data_encin_ff_CQZ_67_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(59) D=top_1.data_encin_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(59) I3=top_0.reset O=top_1.data_encin_ff_CQZ_68_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(58) D=top_1.data_encin_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(58) I3=top_0.reset O=top_1.data_encin_ff_CQZ_69_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(121) I3=top_0.reset O=top_1.data_encin_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(120) D=top_1.data_encin_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(57) D=top_1.data_encin_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(57) I3=top_0.reset O=top_1.data_encin_ff_CQZ_70_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(56) D=top_1.data_encin_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(56) I3=top_0.reset O=top_1.data_encin_ff_CQZ_71_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(55) D=top_1.data_encin_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(55) I3=top_0.reset O=top_1.data_encin_ff_CQZ_72_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(54) D=top_1.data_encin_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(54) I3=top_0.reset O=top_1.data_encin_ff_CQZ_73_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(53) D=top_1.data_encin_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(53) I3=top_0.reset O=top_1.data_encin_ff_CQZ_74_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(52) D=top_1.data_encin_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(52) I3=top_0.reset O=top_1.data_encin_ff_CQZ_75_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(51) D=top_1.data_encin_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(51) I3=top_0.reset O=top_1.data_encin_ff_CQZ_76_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(50) D=top_1.data_encin_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(50) I3=top_0.reset O=top_1.data_encin_ff_CQZ_77_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(49) D=top_1.data_encin_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(49) I3=top_0.reset O=top_1.data_encin_ff_CQZ_78_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(48) D=top_1.data_encin_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(48) I3=top_0.reset O=top_1.data_encin_ff_CQZ_79_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(120) I3=top_0.reset O=top_1.data_encin_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(119) D=top_1.data_encin_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(47) D=top_1.data_encin_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(47) I3=top_0.reset O=top_1.data_encin_ff_CQZ_80_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(46) D=top_1.data_encin_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(46) I3=top_0.reset O=top_1.data_encin_ff_CQZ_81_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(45) D=top_1.data_encin_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(45) I3=top_0.reset O=top_1.data_encin_ff_CQZ_82_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(44) D=top_1.data_encin_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(44) I3=top_0.reset O=top_1.data_encin_ff_CQZ_83_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(43) D=top_1.data_encin_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(43) I3=top_0.reset O=top_1.data_encin_ff_CQZ_84_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(42) D=top_1.data_encin_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(42) I3=top_0.reset O=top_1.data_encin_ff_CQZ_85_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(41) D=top_1.data_encin_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(41) I3=top_0.reset O=top_1.data_encin_ff_CQZ_86_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(40) D=top_1.data_encin_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(40) I3=top_0.reset O=top_1.data_encin_ff_CQZ_87_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(39) D=top_1.data_encin_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(39) I3=top_0.reset O=top_1.data_encin_ff_CQZ_88_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(38) D=top_1.data_encin_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(38) I3=top_0.reset O=top_1.data_encin_ff_CQZ_89_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(119) I3=top_0.reset O=top_1.data_encin_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(118) D=top_1.data_encin_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.U01.datain(37) D=top_1.data_encin_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(37) I3=top_0.reset O=top_1.data_encin_ff_CQZ_90_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(36) D=top_1.data_encin_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(36) I3=top_0.reset O=top_1.data_encin_ff_CQZ_91_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(35) D=top_1.data_encin_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(35) I3=top_0.reset O=top_1.data_encin_ff_CQZ_92_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(34) D=top_1.data_encin_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(34) I3=top_0.reset O=top_1.data_encin_ff_CQZ_93_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(33) D=top_1.data_encin_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(33) I3=top_0.reset O=top_1.data_encin_ff_CQZ_94_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(32) D=top_1.data_encin_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(32) I3=top_0.reset O=top_1.data_encin_ff_CQZ_95_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(31) D=top_1.data_encin_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(31) I3=top_0.reset O=top_1.data_encin_ff_CQZ_96_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(30) D=top_1.data_encin_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(30) I3=top_0.reset O=top_1.data_encin_ff_CQZ_97_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(29) D=top_1.data_encin_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(29) I3=top_0.reset O=top_1.data_encin_ff_CQZ_98_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.U01.datain(28) D=top_1.data_encin_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(28) I3=top_0.reset O=top_1.data_encin_ff_CQZ_99_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(118) I3=top_0.reset O=top_1.data_encin_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(127) I3=top_0.reset O=top_1.data_encin_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=top_1.data_encout1(6) D=top_1.data_encout1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout1(5) D=top_1.data_encout1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout1(4) D=top_1.data_encout1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout1(3) D=top_1.data_encout1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout1(2) D=top_1.data_encout1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout1(1) D=top_1.data_encout1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout1(0) D=top_1.data_encout1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111001011111111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3 O=top_1.data_encout1_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(39) I1=top_1.U011.datain(38) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U011.datain(103) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.U011.datain(102) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I2=top_1.U011.datain(96) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.U011.datain(119) I2=top_1.U011.datain(118) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_1.U011.datain(122) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(123) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.U011.datain(107) I3=top_1.U011.datain(106) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U011.datain(104) I1=top_1.U011.datain(105) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(108) I1=top_1.U011.datain(111) I2=top_1.U011.datain(110) I3=top_1.U011.datain(109) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U011.datain(97) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U011.datain(96) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.U011.datain(97) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(99) I1=top_1.U011.datain(98) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(105) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(104) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(108) I3=top_1.U011.datain(109) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(81) I1=top_1.U011.datain(80) I2=top_1.U011.datain(83) I3=top_1.U011.datain(82) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_1.U011.datain(82) I1=top_1.U011.datain(81) I2=top_1.U011.datain(80) I3=top_1.U011.datain(83) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(112) I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U011.datain(113) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 I3=top_1.U011.datain(112) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I2=top_1.U011.datain(114) I3=top_1.U011.datain(115) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=top_1.U011.datain(67) I1=top_1.U011.datain(66) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(71) I1=top_1.U011.datain(70) I2=top_1.U011.datain(69) I3=top_1.U011.datain(68) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(100) I3=top_1.U011.datain(101) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(98) I3=top_1.U011.datain(99) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(98) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.U011.datain(99) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(96) I3=top_1.U011.datain(97) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(67) I3=top_1.U011.datain(66) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(64) I3=top_1.U011.datain(65) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(117) I1=top_0.reset I2=top_1.U011.datain(116) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(121) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(120) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(109) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U011.datain(108) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(110) I3=top_1.U011.datain(111) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(104) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.U011.datain(105) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(106) I3=top_1.U011.datain(107) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(95) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_1.U011.datain(94) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(93) I3=top_1.U011.datain(92) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(55) I1=top_1.U011.datain(53) I2=top_1.U011.datain(52) I3=top_1.U011.datain(54) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(118) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.U011.datain(119) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(116) I3=top_1.U011.datain(117) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(117) I1=top_1.U011.datain(116) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(115) I1=top_1.U011.datain(114) I2=top_1.U011.datain(113) I3=top_1.U011.datain(112) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=top_1.U011.datain(87) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.U011.datain(86) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(65) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=top_1.U011.datain(64) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(99) I3=top_1.U011.datain(98) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3 O=top_1.data_encout1_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(56) I1=top_0.reset I2=top_1.U011.datain(57) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(89) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.U011.datain(88) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(90) I3=top_1.U011.datain(91) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(92) I1=top_1.U011.datain(95) I2=top_1.U011.datain(94) I3=top_1.U011.datain(93) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U011.datain(24) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=top_1.U011.datain(25) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(26) I3=top_1.U011.datain(27) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(16) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.U011.datain(17) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(18) I3=top_1.U011.datain(19) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(17) I1=top_0.reset I2=top_1.U011.datain(16) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(60) I1=top_0.reset I2=top_1.U011.datain(61) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U011.datain(62) I3=top_1.U011.datain(63) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(28) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I3=top_1.U011.datain(29) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(30) I3=top_1.U011.datain(31) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(24) I1=top_1.U011.datain(27) I2=top_1.U011.datain(26) I3=top_1.U011.datain(25) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(3) I1=top_1.U011.datain(2) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(7) I1=top_1.U011.datain(6) I2=top_1.U011.datain(5) I3=top_1.U011.datain(4) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U011.datain(3) I1=top_1.U011.datain(2) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I2=top_1.U011.datain(3) I3=top_1.U011.datain(2) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(0) I3=top_1.U011.datain(1) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(18) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.U011.datain(19) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(16) I3=top_1.U011.datain(17) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(19) I1=top_1.U011.datain(18) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(23) I1=top_1.U011.datain(22) I2=top_1.U011.datain(21) I3=top_1.U011.datain(20) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(28) I1=top_1.U011.datain(31) I2=top_1.U011.datain(30) I3=top_1.U011.datain(29) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_1.U011.datain(49) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.U011.datain(48) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(35) I3=top_1.U011.datain(34) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(39) I1=top_1.U011.datain(38) I2=top_1.U011.datain(37) I3=top_1.U011.datain(36) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=top_1.U011.datain(50) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.U011.datain(51) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U011.datain(25) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(24) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(28) I3=top_1.U011.datain(29) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U011.datain(89) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(88) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2 I2=top_1.U011.datain(92) I3=top_1.U011.datain(93) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(90) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(91) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(89) I3=top_1.U011.datain(88) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(58) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.U011.datain(59) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(26) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(27) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(25) I3=top_1.U011.datain(24) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=top_1.U011.datain(95) I2=top_1.U011.datain(94) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=top_1.U011.datain(90) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(91) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(83) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(82) I1=top_1.U011.datain(81) I2=top_0.reset I3=top_1.U011.datain(80) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3 O=top_1.data_encout1_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_1.U011.datain(12) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(12) I1=top_1.U011.datain(9) I2=top_1.U011.datain(8) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_1.U011.datain(12) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(13) I2=top_1.U011.datain(14) I3=top_1.U011.datain(15) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(73) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(72) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(8) I1=top_1.U011.datain(10) I2=top_1.U011.datain(9) I3=top_1.U011.datain(11) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_1.U011.datain(31) I1=top_0.reset I2=top_1.U011.datain(30) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_1.U011.datain(47) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I3=top_1.U011.datain(46) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I2=top_1.U011.datain(45) I3=top_1.U011.datain(44) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3 O=top_1.data_encout1_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_1.U011.datain(53) I1=top_0.reset I2=top_1.U011.datain(52) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(85) I1=top_1.U011.datain(84) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(86) I3=top_1.U011.datain(87) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(23) I1=top_1.U011.datain(22) I2=top_1.U011.datain(21) I3=top_1.U011.datain(20) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U011.datain(5) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O I3=top_1.U011.datain(4) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(4) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(5) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(6) I3=top_1.U011.datain(7) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(37) I1=top_0.reset I2=top_1.U011.datain(36) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(38) I3=top_1.U011.datain(39) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(34) I3=top_1.U011.datain(35) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(71) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U011.datain(70) I1=top_1.U011.datain(69) I2=top_0.reset I3=top_1.U011.datain(68) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(101) I1=top_0.reset I2=top_1.U011.datain(100) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_1.data_encout1_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(72) I1=top_1.U011.datain(75) I2=top_1.U011.datain(73) I3=top_1.U011.datain(74) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(90) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.U011.datain(91) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U011.datain(27) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=top_1.U011.datain(26) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(8) I1=top_1.U011.datain(11) I2=top_1.U011.datain(9) I3=top_1.U011.datain(10) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(19) I1=top_0.reset I2=top_1.U011.datain(18) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(2) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I3=top_1.U011.datain(3) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(22) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U011.datain(23) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(6) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O I3=top_1.U011.datain(7) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(70) I2=top_0.reset I3=top_1.U011.datain(71) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_1.data_encout1_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_1.U011.datain(85) I3=top_1.U011.datain(84) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(23) I1=top_1.U011.datain(22) I2=top_1.U011.datain(20) I3=top_1.U011.datain(21) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(19) I1=top_1.U011.datain(18) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(8) I1=top_1.U011.datain(11) I2=top_1.U011.datain(10) I3=top_1.U011.datain(9) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(14) I3=top_1.U011.datain(15) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(13) I2=top_0.reset I3=top_1.U011.datain(12) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(71) I1=top_1.U011.datain(70) I2=top_1.U011.datain(68) I3=top_1.U011.datain(69) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(45) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=top_1.U011.datain(44) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U011.datain(76) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_1.U011.datain(48) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(49) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=top_1.U011.datain(50) I3=top_1.U011.datain(51) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(80) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(81) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(82) I3=top_1.U011.datain(83) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(72) I1=top_1.U011.datain(74) I2=top_1.U011.datain(73) I3=top_1.U011.datain(75) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U011.datain(76) I1=top_1.U011.datain(79) I2=top_1.U011.datain(78) I3=top_1.U011.datain(77) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_1.U011.datain(42) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(43) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.U011.datain(72) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(73) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(74) I3=top_1.U011.datain(75) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(64) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(65) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(66) I3=top_1.U011.datain(67) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(67) I1=top_1.U011.datain(66) I2=top_1.U011.datain(65) I3=top_1.U011.datain(64) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(83) I1=top_1.U011.datain(82) I2=top_1.U011.datain(81) I3=top_1.U011.datain(80) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(32) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_1.U011.datain(33) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(3) I1=top_1.U011.datain(2) I2=top_1.U011.datain(0) I3=top_1.U011.datain(1) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(8) I1=top_0.reset I2=top_1.U011.datain(9) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(10) I3=top_1.U011.datain(11) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110100
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(106) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.U011.datain(107) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2 I3=top_1.U011.datain(77) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010001000
|
|
.subckt LUT4 I0=top_1.U011.datain(72) I1=top_1.U011.datain(75) I2=top_1.U011.datain(74) I3=top_1.U011.datain(73) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2 I2=top_1.U011.datain(76) I3=top_1.U011.datain(77) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.U011.datain(78) I3=top_1.U011.datain(79) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(79) I3=top_1.U011.datain(78) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(78) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 I3=top_1.U011.datain(79) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.U011.datain(77) I3=top_1.U011.datain(76) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(46) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(47) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(111) I3=top_1.U011.datain(110) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(109) I3=top_1.U011.datain(108) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(104) I1=top_1.U011.datain(107) I2=top_1.U011.datain(106) I3=top_1.U011.datain(105) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=top_1.U011.datain(30) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(31) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(29) I3=top_1.U011.datain(28) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(94) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(95) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(38) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(39) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U011.datain(37) I1=top_1.U011.datain(36) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(102) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(103) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=top_1.U011.datain(86) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(87) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(84) I3=top_1.U011.datain(85) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_1.U011.datain(14) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(15) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(15) I1=top_0.reset I2=top_1.U011.datain(14) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(13) I3=top_1.U011.datain(12) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(70) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(71) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(68) I3=top_1.U011.datain(69) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_1.U011.datain(6) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O I2=top_1.U011.datain(7) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I2=top_1.U011.datain(4) I3=top_1.U011.datain(5) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(23) I3=top_1.U011.datain(22) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(20) I3=top_1.U011.datain(21) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(93) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2 I3=top_1.U011.datain(92) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(94) I3=top_1.U011.datain(95) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(88) I1=top_1.U011.datain(91) I2=top_1.U011.datain(90) I3=top_1.U011.datain(89) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U011.datain(124) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(125) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(124) I3=top_1.U011.datain(125) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(127) I3=top_1.U011.datain(126) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(120) I1=top_1.U011.datain(123) I2=top_1.U011.datain(122) I3=top_1.U011.datain(121) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(112) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.U011.datain(113) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(52) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(53) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(52) I3=top_1.U011.datain(53) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(54) I3=top_1.U011.datain(55) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(63) I3=top_1.U011.datain(62) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U011.datain(60) I1=top_1.U011.datain(61) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(56) I1=top_1.U011.datain(59) I2=top_1.U011.datain(58) I3=top_1.U011.datain(57) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I2=top_1.U011.datain(119) I3=top_1.U011.datain(118) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(54) I1=top_1.U011.datain(53) I2=top_1.U011.datain(52) I3=top_1.U011.datain(55) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U011.datain(126) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(127) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(125) I3=top_1.U011.datain(124) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.U011.datain(37) I3=top_1.U011.datain(36) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U011.datain(100) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(101) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(102) I3=top_1.U011.datain(103) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U011.datain(59) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_1.U011.datain(58) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(57) I3=top_1.U011.datain(56) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U011.datain(123) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(122) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_1.U011.datain(116) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 I2=top_1.U011.datain(117) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(117) I1=top_1.U011.datain(116) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(124) I1=top_1.U011.datain(126) I2=top_1.U011.datain(125) I3=top_1.U011.datain(127) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(118) I3=top_1.U011.datain(119) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(114) I1=top_1.U011.datain(113) I2=top_1.U011.datain(112) I3=top_1.U011.datain(115) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.U011.datain(51) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(50) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.U011.datain(50) I3=top_1.U011.datain(51) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(48) I3=top_1.U011.datain(49) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U011.datain(60) I1=top_1.U011.datain(63) I2=top_1.U011.datain(62) I3=top_1.U011.datain(61) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(113) I1=top_1.U011.datain(112) I2=top_1.U011.datain(115) I3=top_1.U011.datain(114) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U011.datain(35) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100001100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(34) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(32) I3=top_1.U011.datain(33) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U011.datain(45) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(44) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I2=top_1.U011.datain(46) I3=top_1.U011.datain(47) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(40) I3=top_1.U011.datain(41) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=top_1.U011.datain(57) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(56) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(58) I3=top_1.U011.datain(59) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(60) I3=top_1.U011.datain(61) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U011.datain(127) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.U011.datain(126) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(63) I1=top_0.reset I2=top_1.U011.datain(62) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U011.datain(40) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.U011.datain(41) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.U011.datain(42) I3=top_1.U011.datain(43) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_1.U011.datain(43) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I3=top_1.U011.datain(42) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(40) I1=top_1.U011.datain(41) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(44) I1=top_1.U011.datain(47) I2=top_1.U011.datain(46) I3=top_1.U011.datain(45) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=top_1.U011.datain(120) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(121) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(122) I3=top_1.U011.datain(123) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(110) I3=top_1.U011.datain(111) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_1.U011.datain(33) I1=top_0.reset I2=top_1.U011.datain(32) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U011.datain(40) I1=top_1.U011.datain(43) I2=top_1.U011.datain(42) I3=top_1.U011.datain(41) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(34) I3=top_1.U011.datain(35) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U011.datain(122) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(123) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(121) I3=top_1.U011.datain(120) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=top_1.data_encout(6) D=top_1.data_encout_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout(5) D=top_1.data_encout_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout(4) D=top_1.data_encout_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout(3) D=top_1.data_encout_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout(2) D=top_1.data_encout_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout(1) D=top_1.data_encout_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_1.data_encout(0) D=top_1.data_encout_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3 O=top_1.data_encout_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(123) I3=top_1.U01.datain(122) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(63) I3=top_1.U01.datain(62) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(61) I3=top_1.U01.datain(60) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(110) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(111) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(109) I3=top_1.U01.datain(108) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(104) I1=top_1.U01.datain(107) I2=top_1.U01.datain(106) I3=top_1.U01.datain(105) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_1.U01.datain(98) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_1.U01.datain(99) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(35) I2=top_0.reset I3=top_1.U01.datain(34) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(32) I3=top_1.U01.datain(33) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(102) I1=top_1.U01.datain(101) I2=top_1.U01.datain(100) I3=top_1.U01.datain(103) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U01.datain(39) I1=top_0.reset I2=top_1.U01.datain(38) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(36) I3=top_1.U01.datain(37) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011101110000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3 O=top_1.data_encout_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=top_1.U01.datain(49) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.U01.datain(48) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(51) I1=top_1.U01.datain(50) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111111111000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(114) I1=top_1.U01.datain(113) I2=top_1.U01.datain(112) I3=top_1.U01.datain(115) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(118) I3=top_1.U01.datain(119) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(115) I1=top_1.U01.datain(113) I2=top_1.U01.datain(112) I3=top_1.U01.datain(114) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(80) I1=top_1.U01.datain(83) I2=top_1.U01.datain(81) I3=top_1.U01.datain(82) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(87) I1=top_1.U01.datain(86) I2=top_1.U01.datain(85) I3=top_1.U01.datain(84) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(61) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(60) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(62) I3=top_1.U01.datain(63) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(51) I1=top_0.reset I2=top_1.U01.datain(50) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(48) I3=top_1.U01.datain(49) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(51) I3=top_1.U01.datain(50) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(52) I3=top_1.U01.datain(53) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(60) I1=top_1.U01.datain(63) I2=top_1.U01.datain(62) I3=top_1.U01.datain(61) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(56) I1=top_1.U01.datain(59) I2=top_1.U01.datain(58) I3=top_1.U01.datain(57) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3 O=top_1.data_encout_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110100
|
|
.subckt LUT4 I0=top_1.U01.datain(25) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(24) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(26) I3=top_1.U01.datain(27) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(28) I1=top_1.U01.datain(31) I2=top_1.U01.datain(30) I3=top_1.U01.datain(29) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(28) I3=top_1.U01.datain(29) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(30) I3=top_1.U01.datain(31) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U01.datain(57) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(56) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(60) I3=top_1.U01.datain(61) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_1.U01.datain(40) I1=top_0.reset I2=top_1.U01.datain(41) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=top_1.U01.datain(42) I3=top_1.U01.datain(43) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(56) I1=top_0.reset I2=top_1.U01.datain(57) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(58) I3=top_1.U01.datain(59) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_I2_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(122) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(123) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(121) I3=top_1.U01.datain(120) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(88) I1=top_0.reset I2=top_1.U01.datain(89) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(90) I3=top_1.U01.datain(91) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(24) I1=top_0.reset I2=top_1.U01.datain(25) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U01.datain(72) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(73) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(72) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(73) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(75) I3=top_1.U01.datain(74) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(79) I1=top_1.U01.datain(78) I2=top_1.U01.datain(77) I3=top_1.U01.datain(76) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=top_1.U01.datain(41) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(40) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(44) I3=top_1.U01.datain(45) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_1.U01.datain(13) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(12) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(59) I1=top_0.reset I2=top_1.U01.datain(58) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(91) I1=top_0.reset I2=top_1.U01.datain(90) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(89) I3=top_1.U01.datain(88) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(26) I2=top_0.reset I3=top_1.U01.datain(27) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(25) I3=top_1.U01.datain(24) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3 O=top_1.data_encout_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(5) I1=top_1.U01.datain(4) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U01.datain(7) I1=top_1.U01.datain(6) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(4) I3=top_1.U01.datain(5) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(3) I1=top_1.U01.datain(2) I2=top_1.U01.datain(1) I3=top_1.U01.datain(0) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(8) I1=top_1.U01.datain(11) I2=top_1.U01.datain(9) I3=top_1.U01.datain(10) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(71) I2=top_1.U01.datain(70) I3=top_1.U01.datain(68) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111110110000
|
|
.subckt LUT4 I0=top_1.U01.datain(37) I1=top_1.U01.datain(36) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(38) I3=top_1.U01.datain(39) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=top_1.U01.datain(119) I1=top_1.U01.datain(118) I2=top_1.U01.datain(116) I3=top_1.U01.datain(117) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(21) I1=top_0.reset I2=top_1.U01.datain(20) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(53) I1=top_0.reset I2=top_1.U01.datain(52) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3 O=top_1.data_encout_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_1.U01.datain(43) I1=top_0.reset I2=top_1.U01.datain(42) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_1.U01.datain(66) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 I2=top_1.U01.datain(67) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(68) I2=top_1.U01.datain(71) I3=top_1.U01.datain(70) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(67) I1=top_0.reset I2=top_1.U01.datain(66) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(64) I3=top_1.U01.datain(65) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(75) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(74) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(72) I3=top_1.U01.datain(73) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_1.U01.datain(11) I1=top_1.U01.datain(9) I2=top_1.U01.datain(10) I3=top_1.U01.datain(8) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U01.datain(11) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=top_1.U01.datain(10) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(9) I3=top_1.U01.datain(8) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(19) I1=top_1.U01.datain(18) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U01.datain(16) I1=top_1.U01.datain(17) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(2) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_1.U01.datain(3) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(35) I1=top_0.reset I2=top_1.U01.datain(34) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(63) I1=top_0.reset I2=top_1.U01.datain(62) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(50) I3=top_1.U01.datain(51) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(54) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(55) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U01.datain(47) I1=top_1.U01.datain(46) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U01.datain(79) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_1.U01.datain(78) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(77) I1=top_1.U01.datain(76) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U01.datain(74) I1=top_1.U01.datain(73) I2=top_1.U01.datain(72) I3=top_1.U01.datain(75) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(30) I2=top_0.reset I3=top_1.U01.datain(31) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(23) I1=top_0.reset I2=top_1.U01.datain(22) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(7) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(6) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(14) I2=top_0.reset I3=top_1.U01.datain(15) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3 O=top_1.data_encout_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(30) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(31) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.U01.datain(28) I1=top_1.U01.datain(29) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(24) I1=top_1.U01.datain(27) I2=top_1.U01.datain(26) I3=top_1.U01.datain(25) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(47) I3=top_1.U01.datain(46) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U01.datain(44) I1=top_1.U01.datain(45) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(86) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(87) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U01.datain(38) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.U01.datain(39) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(20) I3=top_1.U01.datain(21) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(23) I2=top_0.reset I3=top_1.U01.datain(22) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(15) I2=top_0.reset I3=top_1.U01.datain(14) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(13) I3=top_1.U01.datain(12) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(6) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(7) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(27) I3=top_1.U01.datain(26) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(58) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(59) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(57) I3=top_1.U01.datain(56) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(75) I2=top_0.reset I3=top_1.U01.datain(74) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(3) I3=top_1.U01.datain(2) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(19) I3=top_1.U01.datain(18) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(10) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(11) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(80) I1=top_1.U01.datain(82) I2=top_1.U01.datain(81) I3=top_1.U01.datain(83) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(48) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(49) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(80) I1=top_0.reset I2=top_1.U01.datain(81) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(82) I3=top_1.U01.datain(83) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(92) I1=top_1.U01.datain(95) I2=top_1.U01.datain(94) I3=top_1.U01.datain(93) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000011111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(18) I3=top_1.U01.datain(19) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(17) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(16) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U01.datain(17) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(16) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(18) I3=top_1.U01.datain(19) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(23) I1=top_1.U01.datain(22) I2=top_1.U01.datain(21) I3=top_1.U01.datain(20) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(3) I1=top_1.U01.datain(2) I2=top_1.U01.datain(0) I3=top_1.U01.datain(1) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(0) I3=top_1.U01.datain(1) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(7) I1=top_1.U01.datain(6) I2=top_1.U01.datain(5) I3=top_1.U01.datain(4) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(12) I1=top_1.U01.datain(15) I2=top_1.U01.datain(13) I3=top_1.U01.datain(14) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(8) I1=top_1.U01.datain(11) I2=top_1.U01.datain(10) I3=top_1.U01.datain(9) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_1.U01.datain(32) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(33) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(33) I1=top_0.reset I2=top_1.U01.datain(32) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(34) I3=top_1.U01.datain(35) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(39) I1=top_1.U01.datain(38) I2=top_1.U01.datain(37) I3=top_1.U01.datain(36) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(34) I3=top_1.U01.datain(35) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(40) I1=top_1.U01.datain(43) I2=top_1.U01.datain(42) I3=top_1.U01.datain(41) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(44) I1=top_1.U01.datain(47) I2=top_1.U01.datain(46) I3=top_1.U01.datain(45) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_1.U01.datain(12) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(13) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(14) I3=top_1.U01.datain(15) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(22) I3=top_1.U01.datain(23) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(16) I1=top_1.U01.datain(19) I2=top_1.U01.datain(18) I3=top_1.U01.datain(17) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(21) I3=top_1.U01.datain(20) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(22) I3=top_1.U01.datain(23) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(68) I2=top_1.U01.datain(71) I3=top_1.U01.datain(70) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(68) I2=top_1.U01.datain(70) I3=top_1.U01.datain(71) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.U01.datain(68) I1=top_1.U01.datain(71) I2=top_1.U01.datain(70) I3=top_1.U01.datain(69) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(5) I3=top_1.U01.datain(4) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=top_1.U01.datain(36) I1=top_1.U01.datain(37) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(28) I1=top_0.reset I2=top_1.U01.datain(29) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=top_1.U01.datain(44) I1=top_0.reset I2=top_1.U01.datain(45) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(46) I3=top_1.U01.datain(47) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(76) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(77) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(78) I3=top_1.U01.datain(79) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_1.U01.datain(54) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(55) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(53) I3=top_1.U01.datain(52) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(54) I3=top_1.U01.datain(55) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(84) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(85) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(87) I1=top_1.U01.datain(86) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110100
|
|
.subckt LUT4 I0=top_1.U01.datain(42) I1=top_1.U01.datain(43) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=top_1.U01.datain(40) I1=top_1.U01.datain(41) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(106) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(107) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(107) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I3=top_1.U01.datain(106) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(105) I3=top_1.U01.datain(104) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(108) I1=top_1.U01.datain(111) I2=top_1.U01.datain(110) I3=top_1.U01.datain(109) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(101) I1=top_1.U01.datain(100) I2=top_1.U01.datain(103) I3=top_1.U01.datain(102) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(96) I3=top_1.U01.datain(97) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(103) I1=top_1.U01.datain(102) I2=top_1.U01.datain(101) I3=top_1.U01.datain(100) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111011101001
|
|
.subckt LUT4 I0=top_1.U01.datain(103) I1=top_1.U01.datain(102) I2=top_1.U01.datain(100) I3=top_1.U01.datain(101) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(92) I1=top_0.reset I2=top_1.U01.datain(93) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(94) I3=top_1.U01.datain(95) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(125) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.U01.datain(124) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(118) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.U01.datain(119) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.U01.datain(119) I1=top_1.U01.datain(118) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(116) I3=top_1.U01.datain(117) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(115) I1=top_1.U01.datain(114) I2=top_1.U01.datain(113) I3=top_1.U01.datain(112) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(87) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.U01.datain(86) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(85) I1=top_1.U01.datain(84) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(80) I1=top_1.U01.datain(83) I2=top_1.U01.datain(82) I3=top_1.U01.datain(81) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=top_1.U01.datain(121) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(120) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(121) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_1.U01.datain(120) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(122) I3=top_1.U01.datain(123) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(124) I1=top_1.U01.datain(126) I2=top_1.U01.datain(127) I3=top_1.U01.datain(125) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(124) I3=top_1.U01.datain(125) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(127) I3=top_1.U01.datain(126) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(120) I1=top_1.U01.datain(123) I2=top_1.U01.datain(122) I3=top_1.U01.datain(121) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(93) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(92) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(88) I3=top_1.U01.datain(89) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(105) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(104) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(108) I3=top_1.U01.datain(109) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(127) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(126) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(95) I3=top_1.U01.datain(94) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(93) I3=top_1.U01.datain(92) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(88) I1=top_1.U01.datain(91) I2=top_1.U01.datain(90) I3=top_1.U01.datain(89) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.U01.datain(104) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I3=top_1.U01.datain(105) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(106) I3=top_1.U01.datain(107) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(98) I3=top_1.U01.datain(99) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(96) I3=top_1.U01.datain(97) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(103) I1=top_1.U01.datain(102) I2=top_1.U01.datain(101) I3=top_1.U01.datain(100) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(97) I2=top_0.reset I3=top_1.U01.datain(96) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(96) I2=top_0.reset I3=top_1.U01.datain(97) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100010000
|
|
.subckt LUT4 I0=top_1.U01.datain(111) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I3=top_1.U01.datain(110) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 I2=top_1.U01.datain(66) I3=top_1.U01.datain(67) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.U01.datain(65) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_1.U01.datain(64) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(77) I1=top_1.U01.datain(76) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(109) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(108) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(110) I3=top_1.U01.datain(111) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(90) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.U01.datain(91) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(64) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(65) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0_LUT4_O_I2 I2=top_1.U01.datain(66) I3=top_1.U01.datain(67) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_1.U01.datain(78) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(79) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=top_1.U01.datain(95) I1=top_0.reset I2=top_1.U01.datain(94) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(127) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(126) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(125) I3=top_1.U01.datain(124) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_1.U01.datain(81) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.U01.datain(80) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(85) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.U01.datain(84) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_1.U01.datain(99) I1=top_0.reset I2=top_1.U01.datain(98) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_1.U01.datain(119) I1=top_1.U01.datain(118) I2=top_1.U01.datain(117) I3=top_1.U01.datain(116) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(119) I3=top_1.U01.datain(118) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(113) I3=top_1.U01.datain(112) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=top_1.U01.datain(118) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(112) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.U01.datain(113) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(114) I3=top_1.U01.datain(115) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=top_2.data_encin1(7) D=top_2.data_encin1_ff_CQZ_D(7) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(6) D=top_2.data_encin1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(5) D=top_2.data_encin1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(4) D=top_2.data_encin1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(3) D=top_2.data_encin1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(2) D=top_2.data_encin1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(1) D=top_2.data_encin1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin1(0) D=top_2.data_encin1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3 O=top_2.data_encin1_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000001110111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(0) I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D(0) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I3=top_1.data_encout1(3) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(3) I3=top_1.data_encout1(2) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10001111
|
|
.subckt LUT4 I0=top_1.data_encout1(0) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100001011
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(2) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3 O=top_2.data_encin1_ff_CQZ_D(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1(1) I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=top_1.data_encout1(1) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(3) I3=top_1.data_encout1(2) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(2) I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(1) I2=top_1.data_encout1(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(6) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100010001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(5) I2=top_1.data_encout1(4) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2 I2=top_0.reset I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(2) I3=top_1.data_encout1(3) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1(0) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin1_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101000000000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D(1) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.reset I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000000000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111111111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D(0) I1=top_1.data_encout1(3) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(1) I2=top_0.reset I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(6) I3=top_1.data_encout1(5) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=top_1.data_encout1(0) I1=top_1.data_encout1(1) I2=top_1.data_encout1(2) I3=top_1.data_encout1(3) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111111111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(3) I3=top_1.data_encout1(2) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=top_1.data_encout1(2) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(1) I2=top_1.data_encout1(0) I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(0) I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(6) I2=top_1.data_encout1(4) I3=top_1.data_encout1(5) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_1.data_encout1(1) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I2=top_1.data_encout1(3) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000011111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I2=top_1.data_encout1(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101111111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1(0) I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100111011000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(6) I2=top_1.data_encout1(5) I3=top_1.data_encout1(4) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000011111111
|
|
.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=top_2.data_encin(7) D=top_2.data_encin_ff_CQZ_D(7) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(6) D=top_2.data_encin_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(5) D=top_2.data_encin_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(4) D=top_2.data_encin_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(3) D=top_2.data_encin_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(2) D=top_2.data_encin_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(1) D=top_2.data_encin_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encin(0) D=top_2.data_encin_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2 I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000001110111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000111111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 I2=top_0.data_encout(0) I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011101000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(0) I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011101110000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=top_0.data_encout(0) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111011111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout(2) I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100111011100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.reset O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3 O=top_2.data_encin_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111111111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111111111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110001
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(0) I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=top_0.data_encout(2) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011010011111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000001000100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=top_0.data_encout(1) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I2=top_0.reset I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1 I2=top_0.data_encout(1) I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111101011001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(2) I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin_ff_CQZ_D(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=top_0.data_encout(2) I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101011101010101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(6) I2=top_0.data_encout(5) I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3 O=top_2.data_encin_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111111111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_0.data_encout(6) O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_0.data_encout(1) I1=top_0.data_encout(0) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_0.data_encout(1) I1=top_0.data_encout(0) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(4) I2=top_0.data_encout(5) I3=top_0.data_encout(6) O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3 O=top_2.data_encin_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(6) I2=top_0.data_encout(4) I3=top_0.data_encout(5) O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.reset O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100010001000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(5) I2=top_0.data_encout(6) I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 I1=top_0.data_encout(6) I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100010001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10001111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3 O=top_2.data_encin_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(3) I2=top_0.data_encout(2) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(1) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=top_0.data_encout(0) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(6) I2=top_0.data_encout(5) I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010001111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(4) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout(4) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(6) I3=top_0.data_encout(5) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_0.data_encout(3) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.data_encout(2) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100001100000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(1) I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout(1) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_0.data_encout(2) I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(2) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(4) I2=top_0.data_encout(6) I3=top_0.data_encout(5) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout(6) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=top_0.data_encout(2) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100001000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=top_2.data_encout1(6) D=top_2.data_encout1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout1(5) D=top_2.data_encout1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout1(4) D=top_2.data_encout1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout1(3) D=top_2.data_encout1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout1(2) D=top_2.data_encout1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout1(1) D=top_2.data_encout1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout1(0) D=top_2.data_encout1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3 O=top_2.data_encout1_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010011111111
|
|
.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(3) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(1) I2=top_2.data_encin1(2) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000101011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(7) I2=top_2.data_encin1(6) I3=top_2.data_encin1(4) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(1) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin1(0) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1(6) I1=top_0.reset I2=top_2.data_encin1(7) I3=top_2.data_encin1(4) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 I2=top_2.data_encin1(5) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_2.data_encin1(5) I1=top_2.data_encin1(4) I2=top_2.data_encin1(7) I3=top_2.data_encin1(6) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0 I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3 O=top_2.data_encout1_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_2.data_encin1(2) I1=top_2.data_encin1(1) I2=top_2.data_encin1(0) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101111111111
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=top_2.data_encin1(6) I1=top_2.data_encin1(7) I2=top_2.data_encin1(5) I3=top_2.data_encin1(4) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_I1_O I1=top_2.data_encin1(3) I2=top_0.reset I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000000101
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3 O=top_2.data_encout1_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1(0) I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_2.data_encin1(0) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encin1(1) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1(7) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001101011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encout1_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 I3=top_2.data_encin1(2) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encin1(1) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(1) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encin1(2) I1=top_2.data_encin1(0) I2=top_2.data_encin1(1) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encin1(3) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I2=top_2.data_encin1(2) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(1) I3=top_2.data_encin1(0) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I2=top_0.reset I3=top_2.data_encin1(1) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(2) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_2.data_encout1_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I2=top_0.reset I3=top_2.data_encin1(7) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111111110001
|
|
.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(2) I2=top_2.data_encin1(1) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encin1(3) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001110101111
|
|
.subckt LUT4 I0=top_2.data_encin1(6) I1=top_2.data_encin1(5) I2=top_2.data_encin1(4) I3=top_2.data_encin1(7) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111110000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(3) I2=top_2.data_encin1(1) I3=top_2.data_encin1(2) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I1=top_2.data_encin1(5) I2=top_2.data_encin1(4) I3=top_2.data_encin1(6) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_2.data_encout1_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(7) I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111111111111
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I1_O O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=top_2.data_encin1(4) I1=top_2.data_encin1(7) I2=top_2.data_encin1(6) I3=top_2.data_encin1(5) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(5) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(0) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I3=top_2.data_encin1(5) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(4) I2=top_2.data_encin1(7) I3=top_2.data_encin1(5) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt ff CQZ=top_2.data_encout(6) D=top_2.data_encout_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout(5) D=top_2.data_encout_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout(4) D=top_2.data_encout_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout(3) D=top_2.data_encout_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout(2) D=top_2.data_encout_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout(1) D=top_2.data_encout_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=top_2.data_encout(0) D=top_2.data_encout_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1 I2=top_2.data_encin(6) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111011111111
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3 O=top_2.data_encout_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010011111111
|
|
.subckt LUT4 I0=top_2.data_encin(3) I1=top_2.data_encin(0) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000011111111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 I1=top_2.data_encin(1) I2=top_2.data_encin(2) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I2_O O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010100000111111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000111111111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011111
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3 O=top_2.data_encout_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000000010001
|
|
.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.reset I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(5) I2=top_2.data_encin(6) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(5) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I1=top_2.data_encin(5) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011000011010101
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin(1) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(4) I2=top_2.data_encin(7) I3=top_2.data_encin(5) O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin(5) O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3 O=top_2.data_encout_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin(3) I1=top_2.data_encin(1) I2=top_2.data_encin(0) I3=top_2.data_encin(2) O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=top_2.data_encin(7) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(1) I2=top_2.data_encin(2) I3=top_2.data_encin(3) O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100010000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111101011000000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I0 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encout_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111111111111
|
|
.subckt LUT4 I0=top_2.data_encin(7) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encin(1) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 I2=top_2.data_encin(1) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(2) I2=top_2.data_encin(3) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000011111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_0.reset I1=top_2.data_encin(7) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=top_2.data_encin(2) I1=top_2.data_encin(1) I2=top_2.data_encin(3) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin(0) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1 O=top_2.data_encout_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(3) I2=top_2.data_encin(2) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3 O=top_2.data_encout_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encin(0) I2=top_0.reset I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin(1) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin(7) I1=top_2.data_encin(4) I2=top_2.data_encin(5) I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encin(2) I1=top_2.data_encin(0) I2=top_2.data_encin(3) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101111
|
|
.subckt LUT4 I0=top_2.data_encin(1) I1=top_2.data_encin(2) I2=top_2.data_encin(3) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=top_0.reset I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000111111111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10111111
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000001110111
|
|
.subckt LUT4 I0=top_2.data_encin(3) I1=top_2.data_encin(2) I2=top_2.data_encin(0) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(2) I2=top_2.data_encin(3) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encin(0) I1=top_0.reset I2=top_2.data_encin(3) I3=top_2.data_encin(2) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(~I0*~I1*I2*I3)"
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.param INIT 0001000000000000
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.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
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.param EQN "(~I0*I1*I2*I3)"
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.param INIT 01000000
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.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(1) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
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.param EQN "(~I0*I1*I2*I3)"
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.param INIT 01000000
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.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(3) I3=top_2.data_encin(2) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
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.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
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.param EQN "(~I0*~I1*I2*I3)"
|
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.param INIT 0001
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.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(7) I3=top_2.data_encin(4) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011101111110000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_I0_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(5) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(4) I2=top_2.data_encin(7) I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=top_2.data_encin(6) I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.end
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