Ganesh Gore 3a472b0db0 [Flow] Adding Makefile for running task		2021-04-03 17:54:59 -06:00
..
arch	Replacing deprecated tile_port syntax	2021-01-12 21:33:53 -08:00
config	[Flow] Adding Makefile for running task	2021-04-03 17:54:59 -06:00
micro_benchmark	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sc_verilog	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
design_variables.yml	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
generate_fabric.openfpga	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
generate_testbench.openfpga	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
process_top_def.sh	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
user_project_wrapper_empty.def	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
user_project_wrapper_template.def	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00