|
SrcLoc, DestLoc
|
|
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
|
|
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
|
|
FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
|