mirror of https://github.com/lnis-uofu/SOFA.git
56 lines
1.7 KiB
Verilog
56 lines
1.7 KiB
Verilog
`timescale 1ns/1ps
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//-----------------------------------------------------
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// Function : An embedded I/O with
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// - An I/O isolation signal to set
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// the I/O in input mode. This is to avoid
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// any unexpected output signals to damage
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// circuits outside the FPGA due to configurable
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// memories are not properly initialized
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// This feature may not be needed if the configurable
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// memory cell has a built-in set/reset functionality
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// - Internal protection circuitry to ensure
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// clean signals at all the SOC I/O ports
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// This is to avoid
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// - output any random signal
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// when the I/O is in input mode, also avoid
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// - driven by any random signal
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// when the I/O is output mode
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//
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// Note: This cell is built with Standard Cells from HD library
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// It is already technology mapped and can be directly used
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// for physical design
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//-----------------------------------------------------
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module QL_CCFF (
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input RESET_B,
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input SE,
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input CFGE,
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input D,
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input SI,
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output Q,
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output CFGQN,
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output CFGQ,
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input CLK
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);
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sky130_fd_sc_hd__nand2_1 NAND2_CFGQN (
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.A(Q),
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.B(CFGE),
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.X(CFGQN)
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);
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sky130_fd_sc_hd__inv_1 INV_CFGQN (
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.A(CFGQN),
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.Y(CFGQ)
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);
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sky130_fd_sc_hd__sdfrtp SDFRTP (
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.Q(Q),
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.CLK(CLK),
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.D(D),
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.SCD(SI),
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.SCE(SE),
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.RESET_B(RESET_B)
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);
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endmodule
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