tangxifan 625ad5e9c6 [HDL] Alpha version of behavioral-level Verilog for SoC wrapper		2020-11-13 18:34:40 -07:00
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caravel_fpga_wrapper.v	[HDL] Alpha version of behavioral-level Verilog for SoC wrapper	2020-11-13 18:34:40 -07:00
digital_io_hd.v	[HDL] Digital I/O of embedded FPGA is now lib independent	2020-11-13 10:00:30 -07:00
skywater_function_verification.v	[HDL] Add preprocessing flags for running functional verification	2020-11-05 11:29:23 -07:00