tangxifan a4f6c34466 [Doc] Add images for multi-mode logic element architecture		2020-11-25 17:17:07 -07:00
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clb_arch.svg	[Doc] Correct bug in I/O circuit design and use svg instead of png in documentation	2020-11-19 16:13:27 -07:00
embedded_io_schematic.svg	[Doc] Correct bug in I/O circuit design and use svg instead of png in documentation	2020-11-19 16:13:27 -07:00
fabric_scan_chain.svg	[Doc] Correct bug in I/O circuit design and use svg instead of png in documentation	2020-11-19 16:13:27 -07:00
fle_arch.svg	[Doc] Add images for multi-mode logic element architecture	2020-11-25 17:17:07 -07:00
fle_arch_dual_lut3_mode.svg	[Doc] Add images for multi-mode logic element architecture	2020-11-25 17:17:07 -07:00
fle_arch_shift_reg_mode.svg	[Doc] Add images for multi-mode logic element architecture	2020-11-25 17:17:07 -07:00
fle_arch_single_lut4_mode.svg	[Doc] Add images for multi-mode logic element architecture	2020-11-25 17:17:07 -07:00
fpga_arch.svg	[Doc] Correct bug in I/O circuit design and use svg instead of png in documentation	2020-11-19 16:13:27 -07:00
fpga_io_map_logic_analyzer_mode.svg	[Doc] Correct bug in I/O circuit design and use svg instead of png in documentation	2020-11-19 16:13:27 -07:00
fpga_io_map_wishbone_mode.svg	[Doc] Minor bug fix in the I/O mapping to wishbone	2020-11-20 18:26:41 -07:00
fpga_io_switch.svg	[Doc] Update I/O resource documentation to synchronize the changes on wrapper	2020-11-20 18:24:29 -07:00