mirror of https://github.com/lnis-uofu/SOFA.git
72 lines
1.5 KiB
Verilog
72 lines
1.5 KiB
Verilog
// Verilog for library /research/ece/lnis/USERS/brown/Skywater/lib/SCRIPTS/liberate/netlists/Verilog/sclib_SKYWATER130_tt created by Liberate 19.2.1.591 on Wed Dec 2 19:03:48 MST 2020 for SDF version 2.1
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// type: scs8hd_muxinv8_1
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`timescale 1ns/10ps
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`celldefine
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module scs8hd_muxinv2_1 (Z, Q1, Q2, S0, S0B, S1, S1B);
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output Z;
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input Q1, Q2, S0, S0B, S1, S1B;
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wire Q1__bar, Q2__bar;
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not (Q2__bar, Q2);
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not (Q1__bar, Q1);
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bufif1 (Z, Q1__bar, S0);
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bufif1 (Z, Q2__bar, S1);
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`ifdef ENABLE_SIGNAL_INITIALIZATION
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initial begin
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$deposit(Q1, 1'b0);
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$deposit(Q2, 1'b0);
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end
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`endif
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specify
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(Q1 => Z) = 0.01;
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(Q2 => Z) = 0.01;
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(S0 => Z) = 0.01;
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(S0B => Z) = 0.01;
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(S1 => Z) = 0.01;
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(S1B => Z) = 0.01;
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endspecify
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endmodule
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`endcelldefine
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// type: scs8hd_muxinv8_1
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`timescale 1ns/10ps
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`celldefine
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module scs8hd_muxinv3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B);
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output Z;
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input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B;
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wire Q1__bar, Q2__bar, Q3__bar;
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not (Q3__bar, Q3);
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not (Q2__bar, Q2);
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not (Q1__bar, Q1);
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bufif1 (Z, Q1__bar, S0);
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bufif1 (Z, Q2__bar, S1);
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bufif1 (Z, Q3__bar, S2);
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`ifdef ENABLE_SIGNAL_INITIALIZATION
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initial begin
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$deposit(Q1, 1'b0);
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$deposit(Q2, 1'b0);
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$deposit(Q3, 1'b0);
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end
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`endif
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// Timing
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specify
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(Q1 => Z) = 0.01;
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(Q3 => Z) = 0.01;
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(S0 => Z) = 0.01;
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(S0B => Z) = 0.01;
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(S2 => Z) = 0.01;
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(S2B => Z) = 0.01;
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endspecify
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endmodule
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`endcelldefine
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