Ganesh Gore 45ff6d2dfe [SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF		2020-12-09 00:54:03 -07:00
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FPGA1212_SOFA_CHD_Verilog	[SOFA_CHD] Removed large testbench file	2020-12-09 00:51:30 -07:00
FPGA1212_SOFA_CHD_task	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
fpga_top	[SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF	2020-12-09 00:54:03 -07:00