mirror of https://github.com/lnis-uofu/SOFA.git
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| .. | ||
| README.md | ||
| caravel_fpga_wrapper_hd.v | ||
| caravel_fpga_wrapper_hd_template.v | ||
| caravel_wrapper_pin_assignment_v1.0.json | ||
| caravel_wrapper_pin_assignment_v1.1.json | ||
| digital_io_hd.v | ||
| sky130_fd_sc_hd_wrapper.v | ||
| skywater_function_verification.v | ||
| wrapper_lines_generator.py | ||
README.md
Skywater PDK
This directory contains the HDL netlists and code generator for FPGA fabrics.
- caravel_fpga_wrapper_hd.v: The wrapper for FPGA fabric to interface the Caravel SoC, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. This file is automatically generated by a Python script
- caravel_defines.v: The parameters required for Caravel wrapper HDL codes
- caravel_fpga_wrapper_hd_template.v: The template HDL codes for the wrapper
- digital_io_hd.v: the I/O cell used by High-density FPGA, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library.
- sky130_fd_sc_hd_wrapper.v: Wrapper codes for the standard cells from the Skywater 130nm Foundry High-Density Standard Cell Library
- skywater_function_verification.v: Include pre-processing flags to enable functional verification for FPGAs
- wrapper_lines_generator.py: Python script to generate the wrapper caravel_fpga_wrapper_hd.v