mirror of https://github.com/lnis-uofu/SOFA.git
114 lines
6.3 KiB
ReStructuredText
114 lines
6.3 KiB
ReStructuredText
.. _qlsofa_hd_io_resource:
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I/O Resources
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-------------
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Pin Assignment
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^^^^^^^^^^^^^^
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The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
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Among the 144 I/Os,
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- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
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- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`qlsofa_hd_io_resource_debug` and :ref:`qlsofa_hd_io_resource_accelerator` for details.
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.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components.
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.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
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.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_qlsofa_hd_fpga_io_switch`.
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.. _fig_qlsofa_hd_fpga_io_switch:
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.. figure:: ./figures/qlsofa_hd_fpga_io_switch.svg
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:scale: 20%
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:alt: I/O arrangement of FPGA IP
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I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
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.. _io_resource_qlsofa_hd_external_io:
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External I/Os
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^^^^^^^^^^^^^
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A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
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Full details are summarized in the following table.
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.. table:: SOFA HD FPGA I/O usage and sizes
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+-----------+------------------------------------------------------------------------+-------------+
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| I/O Type | Description | No. of Pins |
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+===========+========================================================================+=============+
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| Data I/O | Datapath I/Os of FPGA fabric | 27 |
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+-----------+------------------------------------------------------------------------+-------------+
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| CLK | Operating clock of FPGA core | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| RESET | Active-low reset for datapath flip-flops in the FPGA | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| PROG_RESET| Active-low reset for configuration flip-flops in the FPGA | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| CCFF_HEAD | Input of configuation protocol to load bitstream | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| TEST_EN | Activate the test mode of FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| Total | | 37 |
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+-----------+------------------------------------------------------------------------+-------------+
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.. _qlsofa_hd_io_resource_accelerator:
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Accelerator Mode
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^^^^^^^^^^^^^^^^
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When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
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:numref:`fig_qlsofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
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.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.
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.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
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.. _fig_qlsofa_hd_fpga_io_map_wishbone_mode:
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.. figure:: ./figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg
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:scale: 20%
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:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
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I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus
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.. _qlsofa_hd_io_resource_debug:
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Debug Mode
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^^^^^^^^^^
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When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
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:numref:`fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.
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.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
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.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows:
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- all the I/O directionality is set to **input mode**.
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- all the output ports is pulled down to **logic ``0``**.
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.. _fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode:
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.. figure:: ./figures/qlsofa_hd_fpga_io_map_logic_analyzer_mode.svg
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:scale: 20%
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:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
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I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer
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