mirror of https://github.com/lnis-uofu/SOFA.git
132 lines
5.1 KiB
ReStructuredText
132 lines
5.1 KiB
ReStructuredText
.. _qlsofa_hd_clb_arch:
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Configurable Logic Block
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------------------------
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.. _qlsofa_hd_clb_arch_generality:
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Generality
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~~~~~~~~~~
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Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in :numref:`fig_qlsofa_hd_clb_arch`.
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All the pins of the LEs are directly wired to CLB pins without a local routing architecture.
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Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.
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.. _fig_qlsofa_hd_clb_arch:
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.. figure:: ./figures/qlsofa_hd_clb_arch.svg
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:scale: 20%
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:alt: Configurable Logic Block schematic
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Configurable logic block schematic
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.. _qlsofa_hd_clb_arch_le:
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Multi-mode Logic Element
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~~~~~~~~~~~~~~~~~~~~~~~~
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Physical Implementation
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^^^^^^^^^^^^^^^^^^^^^^^
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As shown in :numref:`fig_qlsofa_hd_fle_arch_schematic`, each Logic Element (LE) consists of
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- a fracturable 4-input Look-Up Table (LUT)
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- two D-type Flip-Flops (FF)
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.. _fig_qlsofa_hd_fle_arch_schematic:
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.. figure:: ./figures/qlsofa_hd_fle_arch_schematic.svg
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:scale: 30%
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:alt: Logic element schematic
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Detailed schematic of a logic element
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The LE can operate in different modes to map logic function efficiently
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- 4-input LUT and single FF (see details in :ref:`qlsofa_hd_clb_arch_le_single_lut4_mode`).
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- Dual 3-input LUTs and 2 FFs (see details in :ref:`qlsofa_hd_clb_arch_le_dual_lut3_mode`).
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- 2-bit shift registers (see details in :ref:`qlsofa_hd_clb_arch_le_shift_reg_mode`).
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.. _qlsofa_hd_clb_arch_le_single_lut4_mode:
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Operating mode: LUT4 + FF
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements.
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As depicted in :numref:`fig_qlsofa_hd_fle_arch_single_lut4_mode`, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.
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The operating mode is designed to efficiently implement 4-input functions.
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.. _fig_qlsofa_hd_fle_arch_single_lut4_mode:
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.. figure:: ./figures/qlsofa_hd_fle_arch_single_lut4_mode.svg
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:scale: 30%
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:alt: Logic element schematic
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Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).
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.. _qlsofa_hd_clb_arch_le_dual_lut3_mode:
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Operating mode: Dual-LUT3
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements.
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As depicted in :numref:`fig_qlsofa_hd_fle_arch_dual_lut3_mode`, the fracturable LUT will operate as two 3-input LUTs with shared inputs.
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The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3.
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.. _fig_qlsofa_hd_fle_arch_dual_lut3_mode:
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.. figure:: ./figures/qlsofa_hd_fle_arch_dual_lut3_mode.svg
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:scale: 30%
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:alt: Logic element schematic
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Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).
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.. _qlsofa_hd_clb_arch_le_shift_reg_mode:
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Operating mode: Shift-Register
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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As depicted in :numref:`fig_qlsofa_hd_fle_arch_shift_register_mode`, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.
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The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs.
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.. _fig_qlsofa_hd_fle_arch_shift_register_mode:
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.. figure:: ./figures/qlsofa_hd_fle_arch_shift_register_mode.svg
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:scale: 30%
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:alt: Logic element schematic
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Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).
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.. _qlsofa_hd_clb_arch_le_soft_adder_mode:
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Operating mode: Soft Adder
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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As depicted in :numref:`fig_qlsofa_hd_fle_arch_soft_adder_mode`, the 4-input LUT can implement an 1-bit adder logic, where carry inputs and outputs are connected through dedicated carry chain wires ``cin`` and ``cout`` across logic elements. This is more delay efficient than implementing adders through the dual LUT3 mode (see details in :ref:`qlsofa_hd_clb_arch_le_dual_lut3_mode`).
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The operating mode is designed to efficiently implement multi-bit adders.
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.. _fig_qlsofa_hd_fle_arch_soft_adder_mode:
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.. figure:: ./figures/qlsofa_hd_fle_arch_soft_adder_mode.svg
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:scale: 30%
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:alt: Logic element schematic
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Resource usage of the logic element operating in soft adder mode (Grey blocks and lines are unused resources).
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.. _qlsofa_hd_clb_arch_scan_chain:
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Scan Chain
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~~~~~~~~~~
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There is a built-in scan-chain in the CLB where all the `sc_in` and `sc_out` ports of LEs are connected in a chain, as illustrated in :numref:`fig_qlsofa_hd_clb_arch`.
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When `Test_en` signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain.
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When `Test_en` signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs.
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.. note:: The scan-chain of CLBs are connected in a chain at the top-level. See details in :ref:`qlsofa_hd_fpga_arch_scan_chain`.
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