mirror of https://github.com/lnis-uofu/SOFA.git
24 lines
362 B
Verilog
24 lines
362 B
Verilog
module counter_tb;
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reg clk_counter, rst_counter;
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wire [7:0] q_counter;
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counter_original C_1(
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clk_counter,
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q_counter,
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rst_counter);
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initial begin
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#0 rst_counter = 1'b1; clk_counter = 1'b0;
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#100 rst_counter = 1'b0;
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end
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always begin
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#10 clk_counter = ~clk_counter;
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end
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initial begin
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#5000 $stop;
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end
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endmodule |