mirror of https://github.com/lnis-uofu/SOFA.git
39 lines
1.7 KiB
ReStructuredText
39 lines
1.7 KiB
ReStructuredText
.. _device_resource:
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Device Resources
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----------------
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.. _device_resource_hd_fpga:
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High-Density FPGA
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~~~~~~~~~~~~~~~~~
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The High Density (HD) FPGA is an embedded FPGA built with the Skywater 130nm High Density Standard Cell library (`Sky130_fd_SC_HD <https://cs.opensource.google/skywater-pdk/skywater-pdk/+/master:libraries/sky130_fd_sc_hd/>`_).
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.. table:: Logic capacity of High Density (HD) FPGA IP
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+-------------------------------+------------+
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| Resource Type | Capacity |
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+===============================+============+
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| Look-Up Tables [1]_ | 1152 |
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+-------------------------------+------------+
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| Flip-flops | 2304 |
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+-------------------------------+------------+
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| Max. Configuration Speed [2]_ | 50MHz |
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+-------------------------------+------------+
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| Max. Operating Speed [2]_ | 50MHz |
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+-------------------------------+------------+
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| User I/O Pins [3]_ | 144 |
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+-------------------------------+------------+
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| Max. I/O Speed [2]_ | 33MHz |
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+-------------------------------+------------+
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| Core Voltage | 1.8V |
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+-------------------------------+------------+
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.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
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.. [2] bounded by the maximum speed of `GPIO cells of Skywater 130nm PDK <https://skywater-pdk.readthedocs.io/en/latest/contents/libraries/sky130_fd_io/docs/user_guide.html#design-metrics-1>`_. Higher speed may be expected when a high-speed GPIO cell is available.
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.. [3] I/Os are divided into two groups: GPIO and embedded I/O. See details in :ref:`io_resource`.
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