mirror of https://github.com/lnis-uofu/SOFA.git
76 lines
5.0 KiB
ReStructuredText
76 lines
5.0 KiB
ReStructuredText
.. _dc_ac_character:
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DC and AC Characteristics
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-------------------------
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Each FPGA device contains 37 external I/O pins, whose details are summarized in the following tables.
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I/O usage and port information
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. table:: I/O usage and sizes
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+-----------+------------------------------------------------------------------------+-------------+
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| I/O Type | Description | No. of Pins |
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+===========+========================================================================+=============+
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| Data I/O | Datapath I/Os of FPGA fabric | 29 |
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+-----------+------------------------------------------------------------------------+-------------+
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| Clk | Operating clock of FPGA core | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| CCin | Input of configuation protocol to load bitstream | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| CCout | Output of configuration protocol to read back bitstream | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| TestEn | Activate the test mode of FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
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+-----------+------------------------------------------------------------------------+-------------+
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| Total | | 37 |
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+-----------+------------------------------------------------------------------------+-------------+
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Recommended Operating Conditions
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. table:: Recommended Operating Conditions
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+----------+------------------------------+------+---------+------+-------+
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| Symbol | Description | Min | Typical | Max | Units |
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+==========+==============================+======+=========+======+=======+
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| VDD_io | Supply voltage for I/Os | 1.8 | 3.3 | 5.0 | V |
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+----------+------------------------------+------+---------+------+-------+
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| VDD_core | Supply voltage for FPGA core | 1.62 | 1.8 | 1.98 | V |
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+----------+------------------------------+------+---------+------+-------+
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| V_in | Input voltage for other I/Os | TBD | 3.3 | TBD | V |
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+----------+------------------------------+------+---------+------+-------+
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| I_in | Maximum current through pins | N/A | TBD | TBD | mA |
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+----------+------------------------------+------+---------+------+-------+
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| f_max | Maximum frequency of I/Os | N/A | TBD | TBD | MHz |
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+----------+------------------------------+------+---------+------+-------+
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.. note:: Threshold voltage of logic `1` for I/O (V_OH) is 0.8 * VDD_io. In other words, V_in should be at least 2.64V in order to be sensed as logic `1`
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.. note:: Threshold voltage of logic `0` for I/O (V_OH) is 0.4. In other words, V_in should not exceed 0.4V in order to be sensed as logic `0`.
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Typical AC Characteristics
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. table:: Typical AC characteristics for FPGA I/Os
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+-----------------+-------------------------------------------+------+------+-------+
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| Symbol | Description | Min | Max | Units |
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+=================+===========================================+======+======+=======+
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| V_in Overshoot | Maximum allowed overshoot voltage for Vin | TBD | TBD | V |
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+-----------------+-------------------------------------------+------+------+-------+
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| V_in Undershoot | Minimum allowed overshoot voltage for Vin | TBD | TBD | V |
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+-----------------+-------------------------------------------+------+------+-------+
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| I_VDD_core | Quiescent VDD_core supply current | TBD | TBD | mA |
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+-----------------+-------------------------------------------+------+------+-------+
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| I_VDD_io | Quiescent VDD_io supply current | TBD | TBD | mA |
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+-----------------+-------------------------------------------+------+------+-------+
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