mirror of https://github.com/lnis-uofu/SOFA.git
43 lines
2.1 KiB
Plaintext
43 lines
2.1 KiB
Plaintext
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_130nm/130nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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arch_variable_file=/home/apond/sofa/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=/home/apond/sofa/SCRIPT/openfpga_shell_script/skywater_generate_testbench_arch_exploration.openfpga
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openfpga_arch_file=/home/apond/sofa/ARCH/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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openfpga_sim_setting_file=/home/apond/sofa/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_auto_clock.xml
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openfpga_vpr_device_layout=auto
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openfpga_vpr_route_chan_width=40 # Don't care
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openfpga_verilog_output_dir=/home/apond/sofa/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr
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openfpga_fabric_verilog_netlist=/home/apond/sofa/HDL/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
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external_fabric_key_file=/home/apond/sofa/ARCH/fabric_key/fabric_key_12x12.xml # Don't care
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# Yosys script parameters
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yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
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yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
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[ARCHITECTURES]
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arch0=/home/apond/sofa/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_scan_chain_nonLR_caravel_io_skywater130nm.xml
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[BENCHMARKS]
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bench0=/home/apond/sofa/BENCHMARK/vexriscv/vexriscv_small.v
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[SYNTHESIS_PARAM]
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bench0_top = VexRiscv
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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# none
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