mirror of https://github.com/lnis-uofu/SOFA.git
101 lines
4.3 KiB
Verilog
101 lines
4.3 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// sd_defines.v ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// Description ////
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//// Header file with common definitions ////
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//// ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// Based on original work by ////
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//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
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//// ////
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//// Copyright (C) 2009 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//global defines
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`define BLKSIZE_W 12
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`define BLKCNT_W 16
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//cmd module interrupts
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`define INT_CMD_SIZE 5
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`define INT_CMD_CC 0
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`define INT_CMD_EI 1
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`define INT_CMD_CTE 2
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`define INT_CMD_CCRCE 3
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`define INT_CMD_CIE 4
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//data module interrupts
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`define INT_DATA_SIZE 3
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`define INT_DATA_CC 0
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`define INT_DATA_CCRCE 1
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`define INT_DATA_CFE 2
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//command register defines
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`define CMD_REG_SIZE 14
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`define CMD_RESPONSE_CHECK 1:0
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`define CMD_BUSY_CHECK 2
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`define CMD_CRC_CHECK 3
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`define CMD_IDX_CHECK 4
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`define CMD_WITH_DATA 6:5
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`define CMD_INDEX 13:8
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//register addreses
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`define argument 8'h00
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`define command 8'h04
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`define resp0 8'h08
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`define resp1 8'h0c
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`define resp2 8'h10
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`define resp3 8'h14
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`define controller 8'h1c
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`define timeout 8'h20
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`define clock_d 8'h24
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`define reset 8'h28
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`define voltage 8'h2c
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`define capa 8'h30
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`define cmd_isr 8'h34
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`define cmd_iser 8'h38
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`define data_isr 8'h3c
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`define data_iser 8'h40
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`define blksize 8'h44
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`define blkcnt 8'h48
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`define dst_src_addr 8'h60
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//wb module defines
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`define RESET_BLOCK_SIZE 512
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`define RESET_CLK_DIV 0
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`define SUPPLY_VOLTAGE_mV 3300
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