mirror of https://github.com/lnis-uofu/SOFA.git
127 lines
5.0 KiB
Verilog
127 lines
5.0 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// sd_data_xfer_trig.v ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// Description ////
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//// Module resposible for triggering data transfer based on ////
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//// command transfer completition code ////
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//// ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "sd_defines.v"
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module sd_data_xfer_trig (
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input sd_clk,
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input rst,
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input cmd_with_data_start_i,
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input r_w_i,
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input [`INT_CMD_SIZE-1:0] cmd_int_status_i,
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output reg start_tx_o,
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output reg start_rx_o
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);
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reg r_w_reg;
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parameter SIZE = 2;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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parameter IDLE = 2'b00;
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parameter WAIT_FOR_CMD_INT = 2'b01;
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parameter TRIGGER_XFER = 2'b10;
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always @(state or cmd_with_data_start_i or r_w_i or cmd_int_status_i)
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begin: FSM_COMBO
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case(state)
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IDLE: begin
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if (cmd_with_data_start_i & r_w_i)
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next_state <= TRIGGER_XFER;
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else if (cmd_with_data_start_i)
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next_state <= WAIT_FOR_CMD_INT;
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else
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next_state <= IDLE;
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end
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WAIT_FOR_CMD_INT: begin
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if (cmd_int_status_i[`INT_CMD_CC])
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next_state <= TRIGGER_XFER;
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else if (cmd_int_status_i[`INT_CMD_EI])
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next_state <= IDLE;
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else
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next_state <= WAIT_FOR_CMD_INT;
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end
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TRIGGER_XFER: begin
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next_state <= IDLE;
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end
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default: next_state <= IDLE;
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endcase
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end
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always @(posedge sd_clk or posedge rst)
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begin: FSM_SEQ
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if (rst) begin
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state <= IDLE;
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end
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else begin
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state <= next_state;
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end
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end
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always @(posedge sd_clk or posedge rst)
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begin
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if (rst) begin
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start_tx_o <= 0;
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start_rx_o <= 0;
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r_w_reg <= 0;
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end
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else begin
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case(state)
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IDLE: begin
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start_tx_o <= 0;
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start_rx_o <= 0;
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r_w_reg <= r_w_i;
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end
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WAIT_FOR_CMD_INT: begin
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start_tx_o <= 0;
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start_rx_o <= 0;
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end
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TRIGGER_XFER: begin
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start_tx_o <= ~r_w_reg;
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start_rx_o <= r_w_reg;
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end
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endcase
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end
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end
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endmodule
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