mirror of https://github.com/lnis-uofu/SOFA.git
76 lines
3.7 KiB
Verilog
76 lines
3.7 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// bistable_domain_cross.v ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// Description ////
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//// Clock synchronisation beetween two clock domains. ////
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//// Assumption is that input signal duration has to be at least ////
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//// one clk_b clock period. ////
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//// ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module bistable_domain_cross(
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rst,
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clk_a,
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in,
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clk_b,
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out
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);
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parameter width = 1;
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input rst;
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input clk_a;
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input [width-1:0] in;
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input clk_b;
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output [width-1:0] out;
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// We use a two-stages shift-register to synchronize in to the clk_b clock domain
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reg [width-1:0] sync_clk_b [1:0];
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always @(posedge clk_b or posedge rst)
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begin
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if (rst == 1) begin
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sync_clk_b[0] <= 0;
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sync_clk_b[1] <= 0;
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end else begin
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sync_clk_b[0] <= in;
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sync_clk_b[1] <= sync_clk_b[0];
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end
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end
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assign out = sync_clk_b[1]; // new signal synchronized to (=ready to be used in) clk_b domain
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endmodule
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