mirror of https://github.com/lnis-uofu/SOFA.git
150 lines
5.0 KiB
Verilog
150 lines
5.0 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// JPEG Quantization & Rounding Core ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: jpeg_qnr.v,v 1.3 2002-10-31 12:52:55 rherveille Exp $
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//
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// $Date: 2002-10-31 12:52:55 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/23 09:07:03 rherveille
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// Improved many files.
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// Fixed some bugs in Run-Length-Encoder.
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// Removed dependency on ud_cnt and ro_cnt.
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// Started (Motion)JPEG hardware encoder project.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
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//
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// parameters
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//
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parameter d_width = 12;
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parameter z_width = 2 * d_width;
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//
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// inputs & outputs
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//
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input clk; // system clock
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input ena; // clock enable
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input rst; // asynchronous active low reset
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input dstrb; // present dstrb 1clk cycle before din
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input [d_width-1:0] din; // data input
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input [ 7:0] qnt_val; // quantization value
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output [ 5:0] qnt_cnt; // sample number (get quantization value qnt_cnt)
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output [10:0] dout; // data output
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output douten;
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//
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// variables
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//
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wire [z_width-1:0] iz; // intermediate divident value
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wire [d_width-1:0] id; // intermediate dividor value
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wire [d_width :0] iq; // intermediate result divider
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reg [d_width :0] rq; // rounded q-value
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reg [d_width+3:0] dep;// data enable pipeline
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// generate sample counter
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reg [5:0] qnt_cnt;
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wire dcnt = &qnt_cnt;
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always @(posedge clk or negedge rst)
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if (~rst)
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qnt_cnt <= #1 6'h0;
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else if (dstrb)
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qnt_cnt <= #1 6'h0;
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else if (ena)
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qnt_cnt <= #1 qnt_cnt + 6'h1;
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// generate intermediate dividor/divident values
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assign id = { {(d_width - 8){1'b0}}, qnt_val};
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assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
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// hookup division unit
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div_su #(z_width)
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divider (
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.clk(clk),
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.ena(ena),
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.z(iz),
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.d(id),
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.q(iq),
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.s(),
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.div0(),
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.ovf()
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);
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// round result to the nearest integer
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always @(posedge clk)
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if (ena)
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if (iq[0])
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if (iq[d_width])
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rq <= #1 iq - 1'h1;
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else
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rq <= #1 iq + 1'h1;
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else
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rq <= #1 iq;
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// assign dout signal
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assign dout = rq[d_width -1: d_width-11];
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// generate data-out enable signal
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// This is a pipeline, data is not dependant on sample-count
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integer n;
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always @(posedge clk or negedge rst)
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if (!rst)
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dep <= #1 0;
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else if(ena)
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begin
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dep[0] <= #1 dstrb;
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for (n=1; n <= d_width +3; n = n +1)
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dep[n] <= #1 dep[n-1];
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end
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assign douten = dep[d_width +3];
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endmodule
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