mirror of https://github.com/lnis-uofu/SOFA.git
158 lines
4.6 KiB
Verilog
158 lines
4.6 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Non-restoring signed by unsigned divider ////
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//// Uses the non-restoring unsigned by unsigned divider ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: div_su.v,v 1.3 2002-10-31 12:52:54 rherveille Exp $
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//
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// $Date: 2002-10-31 12:52:54 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/23 09:07:03 rherveille
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// Improved many files.
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// Fixed some bugs in Run-Length-Encoder.
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// Removed dependency on ud_cnt and ro_cnt.
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// Started (Motion)JPEG hardware encoder project.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module div_su(clk, ena, z, d, q, s, div0, ovf);
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//
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// parameters
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//
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parameter z_width = 16;
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parameter d_width = z_width /2;
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//
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// inputs & outputs
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//
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input clk; // system clock
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input ena; // clock enable
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input [z_width-1:0] z; // divident
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input [d_width-1:0] d; // divisor
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output [d_width :0] q; // quotient
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output [d_width-1:0] s; // remainder
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output div0;
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output ovf;
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reg [d_width :0] q;
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reg [d_width-1:0] s;
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reg div0;
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reg ovf;
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//
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// variables
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//
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reg [z_width -1:0] iz;
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reg [d_width -1:0] id;
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reg [d_width +1:0] spipe;
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wire [d_width -1:0] iq, is;
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wire idiv0, iovf;
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//
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// module body
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//
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// delay d
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always @(posedge clk)
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if (ena)
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id <= #1 d;
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// check z, take abs value
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always @(posedge clk)
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if (ena)
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if (z[z_width-1])
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iz <= #1 ~z +1'h1;
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else
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iz <= #1 z;
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// generate spipe (sign bit pipe)
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integer n;
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always @(posedge clk)
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if(ena)
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begin
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spipe[0] <= #1 z[z_width-1];
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for(n=1; n <= d_width+1; n=n+1)
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spipe[n] <= #1 spipe[n-1];
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end
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// hookup non-restoring divider
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div_uu #(z_width, d_width)
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divider (
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.clk(clk),
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.ena(ena),
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.z(iz),
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.d(id),
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.q(iq),
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.s(is),
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.div0(idiv0),
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.ovf(iovf)
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);
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// correct divider results if 'd' was negative
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always @(posedge clk)
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if(ena)
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if(spipe[d_width+1])
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begin
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q <= #1 (~iq) + 1'h1;
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s <= #1 (~is) + 1'h1;
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end
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else
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begin
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q <= #1 {1'b0, iq};
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s <= #1 {1'b0, is};
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end
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// delay flags same as results
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always @(posedge clk)
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if(ena)
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begin
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div0 <= #1 idiv0;
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ovf <= #1 iovf;
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end
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endmodule
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