mirror of https://github.com/lnis-uofu/SOFA.git
4547 lines
518 KiB
Plaintext
4547 lines
518 KiB
Plaintext
# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
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.model jpeg_qnr
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.inputs clk ena rst dstrb din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) din(8) din(9) din(10) din(11) qnt_val(0) qnt_val(1) qnt_val(2) qnt_val(3) qnt_val(4) qnt_val(5) qnt_val(6) qnt_val(7)
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.outputs qnt_cnt(0) qnt_cnt(1) qnt_cnt(2) qnt_cnt(3) qnt_cnt(4) qnt_cnt(5) dout(0) dout(1) dout(2) dout(3) dout(4) dout(5) dout(6) dout(7) dout(8) dout(9) dout(10) douten
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.names $false
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.names $true
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1
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.names $undef
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.subckt logic_0 a=divider.d(10)
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.subckt in_buff A=clk Q=divider.clk
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(0) Q=divider.z(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(1) Q=divider.z(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(10) Q=divider.z(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(11) Q=divider.z(11)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(2) Q=divider.z(2)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(3) Q=divider.z(3)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(4) Q=divider.z(4)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(5) Q=divider.z(5)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(6) Q=divider.z(6)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(7) Q=divider.z(7)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(8) Q=divider.z(8)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=din(9) Q=divider.z(9)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt out_buff A=rq(1) Q=dout(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(2) Q=dout(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(11) Q=dout(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(3) Q=dout(2)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(4) Q=dout(3)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(5) Q=dout(4)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(6) Q=dout(5)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(7) Q=dout(6)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(8) Q=dout(7)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(9) Q=dout(8)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=rq(10) Q=dout(9)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=dep(15) Q=douten
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt in_buff A=dstrb Q=$iopadmap$dstrb
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=ena Q=divider.divider.ena
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt out_buff A=$iopadmap$qnt_cnt(0) Q=qnt_cnt(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=$iopadmap$qnt_cnt(1) Q=qnt_cnt(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=$iopadmap$qnt_cnt(2) Q=qnt_cnt(2)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=$iopadmap$qnt_cnt(3) Q=qnt_cnt(3)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=$iopadmap$qnt_cnt(4) Q=qnt_cnt(4)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=$iopadmap$qnt_cnt(5) Q=qnt_cnt(5)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt in_buff A=qnt_val(0) Q=divider.d(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(1) Q=divider.d(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(2) Q=divider.d(2)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(3) Q=divider.d(3)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(4) Q=divider.d(4)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(5) Q=divider.d(5)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(6) Q=divider.d(6)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=qnt_val(7) Q=divider.d(7)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=rst Q=$iopadmap$rst
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt ff CQZ=dep(14) D=dep(13) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(13) D=dep(12) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(4) D=dep(3) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(3) D=dep(2) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(2) D=dep(1) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(1) D=dep(0) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(0) D=$iopadmap$dstrb QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(12) D=dep(11) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(11) D=dep(10) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(10) D=dep(9) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(9) D=dep(8) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(8) D=dep(7) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(7) D=dep(6) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(6) D=dep(5) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=dep(5) D=dep(4) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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.subckt ff CQZ=divider.divider.d_pipe[10](19) D=divider.divider.d_pipe[9](19) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:144.2-147.39|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
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.subckt ff CQZ=divider.divider.d_pipe[10](18) D=divider.divider.d_pipe[9](18) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:144.2-147.39|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
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.subckt ff CQZ=divider.divider.d_pipe[10](17) D=divider.divider.d_pipe[9](17) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:144.2-147.39|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
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.subckt ff CQZ=divider.divider.q(9) D=divider.divider.q_pipe[11](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
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.subckt ff CQZ=divider.divider.q(8) D=divider.divider.q_pipe[11](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
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.subckt ff CQZ=divider.divider.q(7) D=divider.divider.q_pipe[11](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
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.subckt ff CQZ=divider.divider.q(6) D=divider.divider.q_pipe[11](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
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.subckt ff CQZ=divider.divider.q(5) D=divider.divider.q_pipe[11](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
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.subckt ff CQZ=divider.divider.q(4) D=divider.divider.q_pipe[11](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q(3) D=divider.divider.q_pipe[11](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q(2) D=divider.divider.q_pipe[11](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:192.2-194.56|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](9) D=divider.divider.q_pipe[9](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](8) D=divider.divider.q_pipe[9](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](7) D=divider.divider.q_pipe[9](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
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.attr module_not_derived 00000000000000000000000000000001
|
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](6) D=divider.divider.q_pipe[9](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](5) D=divider.divider.q_pipe[9](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
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.attr module_not_derived 00000000000000000000000000000001
|
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](4) D=divider.divider.q_pipe[9](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
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.attr module_not_derived 00000000000000000000000000000001
|
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](3) D=divider.divider.q_pipe[9](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
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.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](2) D=divider.divider.q_pipe[9](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](1) D=divider.divider.q_pipe[9](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
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.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[10](0) D=divider.divider.q_pipe[10]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[10](24) O=divider.divider.q_pipe[10]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](10) D=divider.divider.q_pipe[10](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](9) D=divider.divider.q_pipe[10](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](0) D=divider.divider.q_pipe[11]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[11](24) O=divider.divider.q_pipe[11]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](8) D=divider.divider.q_pipe[10](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](7) D=divider.divider.q_pipe[10](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](6) D=divider.divider.q_pipe[10](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](5) D=divider.divider.q_pipe[10](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](4) D=divider.divider.q_pipe[10](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](3) D=divider.divider.q_pipe[10](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](2) D=divider.divider.q_pipe[10](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[11](1) D=divider.divider.q_pipe[10](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[1](0) D=divider.divider.q_pipe[1]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[1](24) O=divider.divider.q_pipe[1]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[2](1) D=divider.divider.q_pipe[1](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[2](0) D=divider.divider.q_pipe[2]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[2](24) O=divider.divider.q_pipe[2]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[3](2) D=divider.divider.q_pipe[2](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[3](1) D=divider.divider.q_pipe[2](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[3](0) D=divider.divider.q_pipe[3]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[3](24) O=divider.divider.q_pipe[3]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[4](3) D=divider.divider.q_pipe[3](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[4](2) D=divider.divider.q_pipe[3](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[4](1) D=divider.divider.q_pipe[3](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[4](0) D=divider.divider.q_pipe[4]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[4](24) O=divider.divider.q_pipe[4]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[5](4) D=divider.divider.q_pipe[4](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[5](3) D=divider.divider.q_pipe[4](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[5](2) D=divider.divider.q_pipe[4](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[5](1) D=divider.divider.q_pipe[4](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[5](0) D=divider.divider.q_pipe[5]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[5](24) O=divider.divider.q_pipe[5]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[6](5) D=divider.divider.q_pipe[5](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[6](4) D=divider.divider.q_pipe[5](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[6](3) D=divider.divider.q_pipe[5](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[6](2) D=divider.divider.q_pipe[5](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[6](1) D=divider.divider.q_pipe[5](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[6](0) D=divider.divider.q_pipe[6]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[6](24) O=divider.divider.q_pipe[6]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](6) D=divider.divider.q_pipe[6](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](5) D=divider.divider.q_pipe[6](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](4) D=divider.divider.q_pipe[6](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](3) D=divider.divider.q_pipe[6](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](2) D=divider.divider.q_pipe[6](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](1) D=divider.divider.q_pipe[6](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[7](0) D=divider.divider.q_pipe[7]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[7](24) O=divider.divider.q_pipe[7]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](7) D=divider.divider.q_pipe[7](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](6) D=divider.divider.q_pipe[7](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](5) D=divider.divider.q_pipe[7](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](4) D=divider.divider.q_pipe[7](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](3) D=divider.divider.q_pipe[7](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](2) D=divider.divider.q_pipe[7](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](1) D=divider.divider.q_pipe[7](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[8](0) D=divider.divider.q_pipe[8]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[8](24) O=divider.divider.q_pipe[8]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](8) D=divider.divider.q_pipe[8](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](7) D=divider.divider.q_pipe[8](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](6) D=divider.divider.q_pipe[8](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](5) D=divider.divider.q_pipe[8](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](4) D=divider.divider.q_pipe[8](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](3) D=divider.divider.q_pipe[8](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](2) D=divider.divider.q_pipe[8](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](1) D=divider.divider.q_pipe[8](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.q_pipe[9](0) D=divider.divider.q_pipe[9]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[9](24) O=divider.divider.q_pipe[9]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](24) D=divider.divider.s_pipe[10]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](23) D=divider.divider.s_pipe[10]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](14) D=divider.divider.s_pipe[10]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](13) I2=divider.divider.d_pipe[9](14) I3=divider.divider.s_pipe[10]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](13) D=divider.divider.s_pipe[10]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](12) I2=divider.divider.d_pipe[9](13) I3=divider.divider.s_pipe[10]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[9](12) I2=divider.divider.s_pipe[9](11) I3=divider.divider.s_pipe[9](24) O=divider.divider.s_pipe[10]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](12) D=divider.divider.s_pipe[10]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](11) I3=divider.divider.d_pipe[9](12) O=divider.divider.s_pipe[10]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](11) D=divider.divider.s_pipe[9](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](10) D=divider.divider.s_pipe[9](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](22) I3=divider.divider.s_pipe[10]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[10]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](22) D=divider.divider.s_pipe[10]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[9](21) O=divider.divider.s_pipe[10]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[9](19) I1=divider.divider.s_pipe[9](18) I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[9](20) I3=divider.divider.s_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I1=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[9](20) I3=divider.divider.s_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](21) D=divider.divider.s_pipe[10]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2 I2=divider.divider.s_pipe[9](20) I3=divider.divider.s_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001000111100
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](20) D=divider.divider.s_pipe[10]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](19) I2=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1 O=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[9](18) I3=divider.divider.d_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](19) D=divider.divider.s_pipe[10]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001110101100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](17) I3=divider.divider.d_pipe[9](18) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[9](17) I2=divider.divider.s_pipe[9](16) I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](17) I3=divider.divider.d_pipe[9](18) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[9](18) I3=divider.divider.s_pipe[9](17) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](17) I3=divider.divider.d_pipe[9](18) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](18) I3=divider.divider.d_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](18) D=divider.divider.s_pipe[10]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](17) I2=divider.divider.d_pipe[9](18) I3=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11000101
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](17) D=divider.divider.s_pipe[10]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[9](16) I1=divider.divider.s_pipe[9](15) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[9](16) I1=divider.divider.s_pipe[9](15) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](16) D=divider.divider.s_pipe[10]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[9](16) I3=divider.divider.s_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](14) I3=divider.divider.d_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](14) I3=divider.divider.d_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[10](15) D=divider.divider.s_pipe[10]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](13) I2=divider.divider.d_pipe[9](14) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[9](13) I1=divider.divider.s_pipe[9](12) I2=divider.divider.s_pipe[9](11) I3=divider.divider.d_pipe[9](12) O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](13) I2=divider.divider.d_pipe[9](14) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[9](13) I1=divider.divider.s_pipe[9](12) I2=divider.divider.s_pipe[9](11) I3=divider.divider.d_pipe[9](12) O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[9](14) I2=divider.divider.s_pipe[9](13) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[9](14) I2=divider.divider.s_pipe[9](13) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](14) I3=divider.divider.d_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[9](22) I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[9](23) O=divider.divider.s_pipe[10]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111001000001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I1 I1=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0 I2=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[9](21) O=divider.divider.s_pipe[10]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011100001111
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](24) D=divider.divider.s_pipe[11]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](23) D=divider.divider.s_pipe[11]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](14) D=divider.divider.s_pipe[11]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](13) I2=divider.divider.d_pipe[10](14) I3=divider.divider.s_pipe[11]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I3=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 O=divider.divider.s_pipe[11]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](13) D=divider.divider.s_pipe[11]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](12) I2=divider.divider.d_pipe[10](13) I3=divider.divider.s_pipe[11]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[10](12) I2=divider.divider.s_pipe[10](11) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](12) D=divider.divider.s_pipe[11]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](11) I3=divider.divider.d_pipe[10](12) O=divider.divider.s_pipe[11]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](11) D=divider.divider.s_pipe[10](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](22) I2=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1 I3=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[11]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](22) D=divider.divider.s_pipe[11]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](21) I2=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](20) I2=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[10](19) I2=divider.divider.s_pipe[10](20) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](21) D=divider.divider.s_pipe[11]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](20) I3=divider.divider.s_pipe[11]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[10](19) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101111111111100
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](20) D=divider.divider.s_pipe[11]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[10](24) I3=divider.divider.s_pipe[10](19) O=divider.divider.s_pipe[11]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](19) D=divider.divider.s_pipe[11]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.d_pipe[10](19) I3=divider.divider.s_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](17) I3=divider.divider.d_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[10](19) I1=divider.divider.s_pipe[10](18) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](17) I3=divider.divider.d_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[10](19) I1=divider.divider.s_pipe[10](18) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](18) D=divider.divider.s_pipe[11]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[10](24) I3=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](16) I2=divider.divider.d_pipe[10](17) I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](16) I2=divider.divider.d_pipe[10](17) I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[10](17) I2=divider.divider.s_pipe[10](16) I3=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[10](17) I2=divider.divider.s_pipe[10](16) I3=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](17) I3=divider.divider.d_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](17) D=divider.divider.s_pipe[11]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](16) I2=divider.divider.d_pipe[10](17) I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[10](16) I1=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101011100000001
|
|
.subckt LUT4 I0=divider.divider.d_pipe[10](16) I1=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101100000010
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](16) D=divider.divider.s_pipe[11]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[10](16) I3=divider.divider.s_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](14) I3=divider.divider.d_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[10](14) I2=divider.divider.s_pipe[10](13) I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000101011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](14) I3=divider.divider.d_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[10](15) I3=divider.divider.s_pipe[10](14) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.s_pipe[10](13) I2=divider.divider.d_pipe[10](14) I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](14) I3=divider.divider.d_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=divider.divider.s_pipe[11](15) D=divider.divider.s_pipe[11]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.d_pipe[10](15) I3=divider.divider.s_pipe[10](14) O=divider.divider.s_pipe[11]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[10](14) I2=divider.divider.s_pipe[10](13) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010101100000000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[10](13) I1=divider.divider.s_pipe[10](12) I2=divider.divider.s_pipe[10](11) I3=divider.divider.d_pipe[10](12) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.d_pipe[10](14) I2=divider.divider.s_pipe[10](13) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[10](13) I1=divider.divider.s_pipe[10](12) I2=divider.divider.s_pipe[10](11) I3=divider.divider.d_pipe[10](12) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[10](22) I3=divider.divider.s_pipe[10](23) O=divider.divider.s_pipe[11]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011110111001010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[10](19) I1=divider.divider.s_pipe[10](20) I2=divider.divider.s_pipe[10](21) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=divider.divider.s_pipe[10](20) I3=divider.divider.s_pipe[10](21) O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](24) I3=divider.divider.s_pipe[10](19) O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[12](24) O=divider.divider.q_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=divider.divider.s_pipe[12](24) D=divider.divider.s_pipe[12]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[11](23) O=divider.divider.s_pipe[12]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101111110100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[11](19) I1=divider.divider.s_pipe[11](18) I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100010111
|
|
.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=divider.divider.d_pipe[11](17) I2=divider.divider.s_pipe[11](16) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[11](15) I2=divider.divider.d_pipe[11](16) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00101011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[11](15) I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[11](14) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101010011111101
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](13) I3=divider.divider.d_pipe[11](14) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=divider.divider.d_pipe[11](13) I2=divider.divider.s_pipe[11](12) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000010111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](11) I3=divider.divider.d_pipe[11](12) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](13) I3=divider.divider.d_pipe[11](14) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](17) I3=divider.divider.d_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](17) I3=divider.divider.d_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[11](21) I2=divider.divider.s_pipe[11](22) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[11](24) I2=divider.divider.s_pipe[11](19) I3=divider.divider.s_pipe[11](20) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11](20) I1=divider.divider.s_pipe[11](19) I2=divider.divider.s_pipe[11](24) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[11](19) I1=divider.divider.s_pipe[11](18) I2=divider.divider.s_pipe[11](22) I3=divider.divider.s_pipe[11](21) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11](17) I1=divider.divider.d_pipe[11](18) I2=divider.divider.d_pipe[11](19) I3=divider.divider.s_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000000001011
|
|
.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=divider.divider.s_pipe[11](16) I2=divider.divider.d_pipe[11](17) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[11](16) I2=divider.divider.s_pipe[11](15) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[11](15) I2=divider.divider.s_pipe[11](14) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[11](14) I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[11](13) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010100011111110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[11](12) I2=divider.divider.s_pipe[11](12) I3=divider.divider.s_pipe[11](11) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[11](11) I1=divider.divider.d_pipe[11](12) I2=divider.divider.s_pipe[11](12) I3=divider.divider.d_pipe[11](13) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](17) I3=divider.divider.d_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](24) D=divider.divider.s_pipe[1]_ff_CQZ_D(12) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](23) D=divider.divider.s_pipe[1]_ff_CQZ_D(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](14) D=divider.divider.s_pipe[1]_ff_CQZ_D(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](13) D=divider.divider.s_pipe[1]_ff_CQZ_D(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](12) D=divider.divider.s_pipe[1]_ff_CQZ_D(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](11) D=divider.divider.s_pipe[0](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](10) D=divider.divider.s_pipe[0](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](9) D=divider.divider.s_pipe[0](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](8) D=divider.divider.s_pipe[0](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](7) D=divider.divider.s_pipe[0](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](6) D=divider.divider.s_pipe[0](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](5) D=divider.divider.s_pipe[0](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](22) D=divider.divider.s_pipe[1]_ff_CQZ_D(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](4) D=divider.divider.s_pipe[0](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](3) D=divider.divider.s_pipe[0](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](2) D=divider.divider.s_pipe[0](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](1) D=divider.divider.s_pipe[0](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](21) D=divider.divider.s_pipe[1]_ff_CQZ_D(9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](20) D=divider.divider.s_pipe[1]_ff_CQZ_D(8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](19) D=divider.divider.s_pipe[1]_ff_CQZ_D(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](18) D=divider.divider.s_pipe[1]_ff_CQZ_D(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](17) D=divider.divider.s_pipe[1]_ff_CQZ_D(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](16) D=divider.divider.s_pipe[1]_ff_CQZ_D(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[1](15) D=divider.divider.s_pipe[1]_ff_CQZ_D(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.id_LUT4_I0_O I1=divider.divider.s_pipe[0](22) I2=divider.divider.s_pipe[1]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[0](23) O=divider.divider.s_pipe[1]_ff_CQZ_D(12)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100010000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](22) I2=divider.divider.s_pipe[1]_ff_CQZ_D_LUT4_O_I2 I3=divider.id_LUT4_I0_O O=divider.divider.s_pipe[1]_ff_CQZ_D(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.id_LUT4_I0_O I1=divider.divider.s_pipe[0](19) I2=divider.divider.s_pipe[0](20) I3=divider.divider.s_pipe[0](21) O=divider.divider.s_pipe[1]_ff_CQZ_D(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](20) I2=divider.divider.s_pipe[0](19) I3=divider.id_LUT4_I0_O O=divider.divider.s_pipe[1]_ff_CQZ_D(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](19) I3=divider.id_LUT4_I0_O O=divider.divider.s_pipe[1]_ff_CQZ_D(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](20) I2=divider.divider.s_pipe[0](19) I3=divider.divider.s_pipe[0](21) O=divider.divider.s_pipe[1]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](24) D=divider.divider.s_pipe[2]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](23) D=divider.divider.s_pipe[2]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](14) D=divider.divider.s_pipe[2]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](13) I2=divider.divider.d_pipe[1](14) I3=divider.divider.s_pipe[2]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](13) D=divider.divider.s_pipe[2]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](12) I2=divider.divider.d_pipe[1](13) I3=divider.divider.s_pipe[2]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[1](12) I2=divider.divider.s_pipe[1](11) I3=divider.divider.s_pipe[1](24) O=divider.divider.s_pipe[2]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](12) D=divider.divider.s_pipe[2]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](11) I3=divider.divider.d_pipe[1](12) O=divider.divider.s_pipe[2]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](11) D=divider.divider.s_pipe[1](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](10) D=divider.divider.s_pipe[1](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](9) D=divider.divider.s_pipe[1](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](8) D=divider.divider.s_pipe[1](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](7) D=divider.divider.s_pipe[1](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](6) D=divider.divider.s_pipe[1](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](5) D=divider.divider.s_pipe[1](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](22) I3=divider.divider.s_pipe[2]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[2]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](22) D=divider.divider.s_pipe[2]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](4) D=divider.divider.s_pipe[1](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](3) D=divider.divider.s_pipe[1](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](2) D=divider.divider.s_pipe[1](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[1](21) O=divider.divider.s_pipe[2]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[1](19) I1=divider.divider.s_pipe[1](18) I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[1](20) I3=divider.divider.s_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I1=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[1](20) I3=divider.divider.s_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](21) D=divider.divider.s_pipe[2]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2 I2=divider.divider.s_pipe[1](20) I3=divider.divider.s_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001000111100
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](20) D=divider.divider.s_pipe[2]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](19) I2=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1 O=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[1](18) I3=divider.divider.d_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](19) D=divider.divider.s_pipe[2]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001110101100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](17) I3=divider.divider.d_pipe[1](18) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[1](17) I2=divider.divider.s_pipe[1](16) I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](17) I3=divider.divider.d_pipe[1](18) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[1](18) I3=divider.divider.s_pipe[1](17) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](17) I3=divider.divider.d_pipe[1](18) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](18) I3=divider.divider.d_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](18) D=divider.divider.s_pipe[2]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](17) I2=divider.divider.d_pipe[1](18) I3=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11000101
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](17) D=divider.divider.s_pipe[2]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[1](16) I1=divider.divider.s_pipe[1](15) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[1](16) I1=divider.divider.s_pipe[1](15) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](16) D=divider.divider.s_pipe[2]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[1](16) I3=divider.divider.s_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](14) I3=divider.divider.d_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](14) I3=divider.divider.d_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[2](15) D=divider.divider.s_pipe[2]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](13) I2=divider.divider.d_pipe[1](14) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[1](13) I1=divider.divider.s_pipe[1](12) I2=divider.divider.s_pipe[1](11) I3=divider.divider.d_pipe[1](12) O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](13) I2=divider.divider.d_pipe[1](14) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[1](13) I1=divider.divider.s_pipe[1](12) I2=divider.divider.s_pipe[1](11) I3=divider.divider.d_pipe[1](12) O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[1](14) I2=divider.divider.s_pipe[1](13) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[1](14) I2=divider.divider.s_pipe[1](13) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](14) I3=divider.divider.d_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[1](22) I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[1](23) O=divider.divider.s_pipe[2]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111110110000010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I1 I1=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0 I2=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[1](21) O=divider.divider.s_pipe[2]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](24) D=divider.divider.s_pipe[3]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](23) D=divider.divider.s_pipe[3]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](14) D=divider.divider.s_pipe[3]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](13) I2=divider.divider.d_pipe[2](14) I3=divider.divider.s_pipe[3]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](13) D=divider.divider.s_pipe[3]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](12) I2=divider.divider.d_pipe[2](13) I3=divider.divider.s_pipe[3]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[2](12) I2=divider.divider.s_pipe[2](11) I3=divider.divider.s_pipe[2](24) O=divider.divider.s_pipe[3]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](12) D=divider.divider.s_pipe[3]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](11) I3=divider.divider.d_pipe[2](12) O=divider.divider.s_pipe[3]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](11) D=divider.divider.s_pipe[2](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](10) D=divider.divider.s_pipe[2](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](9) D=divider.divider.s_pipe[2](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](8) D=divider.divider.s_pipe[2](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](7) D=divider.divider.s_pipe[2](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](6) D=divider.divider.s_pipe[2](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](5) D=divider.divider.s_pipe[2](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2 I2=divider.divider.s_pipe[2](21) I3=divider.divider.s_pipe[2](22) O=divider.divider.s_pipe[3]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001110101100
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](22) D=divider.divider.s_pipe[3]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](4) D=divider.divider.s_pipe[2](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](3) D=divider.divider.s_pipe[2](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](21) I2=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[3]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I1=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[2](20) I3=divider.divider.s_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](21) D=divider.divider.s_pipe[3]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2 I2=divider.divider.s_pipe[2](20) I3=divider.divider.s_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001000111100
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](20) D=divider.divider.s_pipe[3]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](19) I2=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1 O=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[2](18) I3=divider.divider.d_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.d_pipe[2](19) I2=divider.divider.s_pipe[2](18) I3=divider.divider.s_pipe[2](24) O=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010000000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](19) D=divider.divider.s_pipe[3]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[2](24) I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001110101100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](17) I2=divider.divider.d_pipe[2](18) I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00101011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[2](18) I3=divider.divider.s_pipe[2](17) O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](17) I3=divider.divider.d_pipe[2](18) O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](18) I3=divider.divider.d_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](18) D=divider.divider.s_pipe[3]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](17) I2=divider.divider.d_pipe[2](18) I3=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](17) D=divider.divider.s_pipe[3]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[2](16) I1=divider.divider.s_pipe[2](15) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[2](16) I1=divider.divider.s_pipe[2](15) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](16) D=divider.divider.s_pipe[3]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[2](16) I3=divider.divider.s_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](14) I3=divider.divider.d_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](14) I3=divider.divider.d_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[3](15) D=divider.divider.s_pipe[3]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[2](24) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](13) I2=divider.divider.d_pipe[2](14) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[2](13) I1=divider.divider.s_pipe[2](12) I2=divider.divider.s_pipe[2](11) I3=divider.divider.d_pipe[2](12) O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](13) I2=divider.divider.d_pipe[2](14) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[2](13) I1=divider.divider.s_pipe[2](12) I2=divider.divider.s_pipe[2](11) I3=divider.divider.d_pipe[2](12) O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[2](14) I2=divider.divider.s_pipe[2](13) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[2](14) I2=divider.divider.s_pipe[2](13) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](14) I3=divider.divider.d_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[2](23) O=divider.divider.s_pipe[3]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.d_pipe[2](19) I2=divider.divider.s_pipe[2](18) I3=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[2](20) I3=divider.divider.s_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](22) I3=divider.divider.s_pipe[2](21) O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2 I2=divider.divider.s_pipe[2](22) I3=divider.divider.s_pipe[2](21) O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](24) D=divider.divider.s_pipe[4]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](23) D=divider.divider.s_pipe[4]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](14) D=divider.divider.s_pipe[4]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](13) I2=divider.divider.d_pipe[3](14) I3=divider.divider.s_pipe[4]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I3=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](13) D=divider.divider.s_pipe[4]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](12) I2=divider.divider.d_pipe[3](13) I3=divider.divider.s_pipe[4]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[3](12) I2=divider.divider.s_pipe[3](11) I3=divider.divider.s_pipe[3](24) O=divider.divider.s_pipe[4]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](12) D=divider.divider.s_pipe[4]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](11) I3=divider.divider.d_pipe[3](12) O=divider.divider.s_pipe[4]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](11) D=divider.divider.s_pipe[3](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](10) D=divider.divider.s_pipe[3](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](9) D=divider.divider.s_pipe[3](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](8) D=divider.divider.s_pipe[3](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](7) D=divider.divider.s_pipe[3](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](6) D=divider.divider.s_pipe[3](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](5) D=divider.divider.s_pipe[3](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](22) I2=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I1 I3=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](22) D=divider.divider.s_pipe[4]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](4) D=divider.divider.s_pipe[3](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[3](21) O=divider.divider.s_pipe[4]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[3](19) I1=divider.divider.s_pipe[3](18) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[3](20) I3=divider.divider.s_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[3](20) I3=divider.divider.s_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](21) D=divider.divider.s_pipe[4]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[3](20) I3=divider.divider.s_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001000111100
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](20) D=divider.divider.s_pipe[4]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](19) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[4]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](24) I3=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](19) D=divider.divider.s_pipe[4]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[3](24) I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](17) I3=divider.divider.d_pipe[3](18) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](17) I3=divider.divider.d_pipe[3](18) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[3](18) I3=divider.divider.d_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](18) I3=divider.divider.d_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](18) D=divider.divider.s_pipe[4]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[3](24) I3=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](16) I2=divider.divider.d_pipe[3](17) I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](16) I2=divider.divider.d_pipe[3](17) I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[3](17) I2=divider.divider.s_pipe[3](16) I3=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[3](17) I2=divider.divider.s_pipe[3](16) I3=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](17) I3=divider.divider.d_pipe[3](18) O=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](17) D=divider.divider.s_pipe[4]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](16) I2=divider.divider.d_pipe[3](17) I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[3](16) I1=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101011100000001
|
|
.subckt LUT4 I0=divider.divider.d_pipe[3](16) I1=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101100000010
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](16) D=divider.divider.s_pipe[4]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[3](16) I3=divider.divider.s_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](14) I3=divider.divider.d_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[3](14) I2=divider.divider.s_pipe[3](13) I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000101011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](14) I3=divider.divider.d_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[3](15) I3=divider.divider.s_pipe[3](14) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.s_pipe[3](13) I2=divider.divider.d_pipe[3](14) I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](14) I3=divider.divider.d_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=divider.divider.s_pipe[4](15) D=divider.divider.s_pipe[4]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.d_pipe[3](15) I3=divider.divider.s_pipe[3](14) O=divider.divider.s_pipe[4]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[3](14) I2=divider.divider.s_pipe[3](13) I3=divider.divider.s_pipe[3](24) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010101100000000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[3](13) I1=divider.divider.s_pipe[3](12) I2=divider.divider.s_pipe[3](11) I3=divider.divider.d_pipe[3](12) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.d_pipe[3](14) I2=divider.divider.s_pipe[3](13) I3=divider.divider.s_pipe[3](24) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[3](13) I1=divider.divider.s_pipe[3](12) I2=divider.divider.s_pipe[3](11) I3=divider.divider.d_pipe[3](12) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[3](23) I3=divider.divider.s_pipe[3](22) O=divider.divider.s_pipe[4]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011110001011010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[3](19) I1=divider.divider.s_pipe[3](20) I2=divider.divider.s_pipe[3](21) I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O O=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](21) I2=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](24) D=divider.divider.s_pipe[5]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](23) D=divider.divider.s_pipe[5]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](14) D=divider.divider.s_pipe[5]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](13) I2=divider.divider.d_pipe[4](14) I3=divider.divider.s_pipe[5]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](13) D=divider.divider.s_pipe[5]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](12) I2=divider.divider.d_pipe[4](13) I3=divider.divider.s_pipe[5]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[4](12) I2=divider.divider.s_pipe[4](11) I3=divider.divider.s_pipe[4](24) O=divider.divider.s_pipe[5]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](12) D=divider.divider.s_pipe[5]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](11) I3=divider.divider.d_pipe[4](12) O=divider.divider.s_pipe[5]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](11) D=divider.divider.s_pipe[4](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](10) D=divider.divider.s_pipe[4](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](9) D=divider.divider.s_pipe[4](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](8) D=divider.divider.s_pipe[4](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](7) D=divider.divider.s_pipe[4](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](6) D=divider.divider.s_pipe[4](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](5) D=divider.divider.s_pipe[4](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[4](21) I2=divider.divider.s_pipe[5]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[4](22) O=divider.divider.s_pipe[5]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[4](21) O=divider.divider.s_pipe[5]_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](22) D=divider.divider.s_pipe[5]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[4](21) O=divider.divider.s_pipe[5]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](20) I3=divider.divider.s_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](21) D=divider.divider.s_pipe[5]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](20) I3=divider.divider.s_pipe[5]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4](24) I1=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011100001111
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](20) D=divider.divider.s_pipe[5]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[4](19) I1=divider.divider.s_pipe[4](18) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](19) D=divider.divider.s_pipe[5]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[4](24) I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](17) I3=divider.divider.d_pipe[4](18) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](17) I3=divider.divider.d_pipe[4](18) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[4](18) I3=divider.divider.d_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](18) I3=divider.divider.d_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](18) D=divider.divider.s_pipe[5]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[4](24) I3=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](16) I2=divider.divider.d_pipe[4](17) I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](16) I2=divider.divider.d_pipe[4](17) I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[4](17) I2=divider.divider.s_pipe[4](16) I3=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[4](17) I2=divider.divider.s_pipe[4](16) I3=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](17) I3=divider.divider.d_pipe[4](18) O=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](17) D=divider.divider.s_pipe[5]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](16) I2=divider.divider.d_pipe[4](17) I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[4](16) I1=divider.divider.s_pipe[4](15) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[4](16) I1=divider.divider.s_pipe[4](15) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](16) D=divider.divider.s_pipe[5]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[4](16) I3=divider.divider.s_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](14) I3=divider.divider.d_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](14) I3=divider.divider.d_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[5](15) D=divider.divider.s_pipe[5]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[4](24) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](13) I2=divider.divider.d_pipe[4](14) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[4](13) I1=divider.divider.s_pipe[4](12) I2=divider.divider.s_pipe[4](11) I3=divider.divider.d_pipe[4](12) O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](13) I2=divider.divider.d_pipe[4](14) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[4](13) I1=divider.divider.s_pipe[4](12) I2=divider.divider.s_pipe[4](11) I3=divider.divider.d_pipe[4](12) O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[4](14) I2=divider.divider.s_pipe[4](13) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[4](14) I2=divider.divider.s_pipe[4](13) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](14) I3=divider.divider.d_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[4](23) O=divider.divider.s_pipe[5]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[4](19) I2=divider.divider.s_pipe[4](20) I3=divider.divider.s_pipe[4](24) O=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](22) I3=divider.divider.s_pipe[4](21) O=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[4](21) I1=divider.divider.s_pipe[4](22) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](24) D=divider.divider.s_pipe[6]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](23) D=divider.divider.s_pipe[6]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](14) D=divider.divider.s_pipe[6]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](13) I2=divider.divider.d_pipe[5](14) I3=divider.divider.s_pipe[6]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I3=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 O=divider.divider.s_pipe[6]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](13) D=divider.divider.s_pipe[6]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](12) I2=divider.divider.d_pipe[5](13) I3=divider.divider.s_pipe[6]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[5](12) I2=divider.divider.s_pipe[5](11) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](12) D=divider.divider.s_pipe[6]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](11) I3=divider.divider.d_pipe[5](12) O=divider.divider.s_pipe[6]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](11) D=divider.divider.s_pipe[5](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](10) D=divider.divider.s_pipe[5](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](9) D=divider.divider.s_pipe[5](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](8) D=divider.divider.s_pipe[5](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](7) D=divider.divider.s_pipe[5](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](6) D=divider.divider.s_pipe[5](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](22) I2=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I1 I3=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[6]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](22) D=divider.divider.s_pipe[6]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](21) I2=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](20) I2=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1 I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O I1=divider.divider.s_pipe[5](20) I2=divider.divider.s_pipe[5](19) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](21) D=divider.divider.s_pipe[6]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1 I2=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I2 I3=divider.divider.s_pipe[5](20) O=divider.divider.s_pipe[6]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](24) I3=divider.divider.s_pipe[5](19) O=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[5](19) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O O=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](20) D=divider.divider.s_pipe[6]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O I2=divider.divider.s_pipe[5](24) I3=divider.divider.s_pipe[5](19) O=divider.divider.s_pipe[6]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](19) D=divider.divider.s_pipe[6]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](18) I2=divider.divider.d_pipe[5](19) I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1 I2=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](17) I3=divider.divider.d_pipe[5](18) O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[5](19) I1=divider.divider.s_pipe[5](18) I2=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1 I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I0 O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](17) I3=divider.divider.d_pipe[5](18) O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](18) D=divider.divider.s_pipe[6]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[5](24) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](16) I2=divider.divider.d_pipe[5](17) I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](16) I2=divider.divider.d_pipe[5](17) I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[5](17) I2=divider.divider.s_pipe[5](16) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[5](17) I2=divider.divider.s_pipe[5](16) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[5](19) I1=divider.divider.s_pipe[5](18) I2=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](17) I3=divider.divider.d_pipe[5](18) O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](17) D=divider.divider.s_pipe[6]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](16) I2=divider.divider.d_pipe[5](17) I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[5](16) I1=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101011100000001
|
|
.subckt LUT4 I0=divider.divider.d_pipe[5](16) I1=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101100000010
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](16) D=divider.divider.s_pipe[6]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[5](16) I3=divider.divider.s_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](14) I3=divider.divider.d_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[5](14) I2=divider.divider.s_pipe[5](13) I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000101011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](14) I3=divider.divider.d_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[5](15) I3=divider.divider.s_pipe[5](14) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.s_pipe[5](13) I2=divider.divider.d_pipe[5](14) I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](14) I3=divider.divider.d_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=divider.divider.s_pipe[6](15) D=divider.divider.s_pipe[6]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.d_pipe[5](15) I3=divider.divider.s_pipe[5](14) O=divider.divider.s_pipe[6]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[5](14) I2=divider.divider.s_pipe[5](13) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010101100000000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[5](13) I1=divider.divider.s_pipe[5](12) I2=divider.divider.s_pipe[5](11) I3=divider.divider.d_pipe[5](12) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.d_pipe[5](14) I2=divider.divider.s_pipe[5](13) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[5](13) I1=divider.divider.s_pipe[5](12) I2=divider.divider.s_pipe[5](11) I3=divider.divider.d_pipe[5](12) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[5](22) I3=divider.divider.s_pipe[5](23) O=divider.divider.s_pipe[6]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011110111001010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O O=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[5](20) I1=divider.divider.s_pipe[5](21) I2=divider.divider.s_pipe[5](19) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1 I2=divider.divider.s_pipe[5](20) I3=divider.divider.s_pipe[5](21) O=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](24) D=divider.divider.s_pipe[7]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](23) D=divider.divider.s_pipe[7]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](14) D=divider.divider.s_pipe[7]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](13) I2=divider.divider.d_pipe[6](14) I3=divider.divider.s_pipe[7]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](13) D=divider.divider.s_pipe[7]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](12) I2=divider.divider.d_pipe[6](13) I3=divider.divider.s_pipe[7]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[6](12) I2=divider.divider.s_pipe[6](11) I3=divider.divider.s_pipe[6](24) O=divider.divider.s_pipe[7]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](12) D=divider.divider.s_pipe[7]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](11) I3=divider.divider.d_pipe[6](12) O=divider.divider.s_pipe[7]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](11) D=divider.divider.s_pipe[6](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](10) D=divider.divider.s_pipe[6](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](9) D=divider.divider.s_pipe[6](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](8) D=divider.divider.s_pipe[6](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](7) D=divider.divider.s_pipe[6](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[6](21) I2=divider.divider.s_pipe[7]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[6](22) O=divider.divider.s_pipe[7]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[6](21) O=divider.divider.s_pipe[7]_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](22) D=divider.divider.s_pipe[7]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[6](21) O=divider.divider.s_pipe[7]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](20) I3=divider.divider.s_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](21) D=divider.divider.s_pipe[7]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](20) I3=divider.divider.s_pipe[7]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6](24) I1=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011100001111
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](20) D=divider.divider.s_pipe[7]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[6](19) I1=divider.divider.s_pipe[6](18) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](19) D=divider.divider.s_pipe[7]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[6](24) I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](17) I3=divider.divider.d_pipe[6](18) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](17) I3=divider.divider.d_pipe[6](18) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[6](18) I3=divider.divider.d_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](18) I3=divider.divider.d_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](18) D=divider.divider.s_pipe[7]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[6](24) I3=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](16) I2=divider.divider.d_pipe[6](17) I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](16) I2=divider.divider.d_pipe[6](17) I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[6](17) I2=divider.divider.s_pipe[6](16) I3=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[6](17) I2=divider.divider.s_pipe[6](16) I3=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](17) I3=divider.divider.d_pipe[6](18) O=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](17) D=divider.divider.s_pipe[7]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](16) I2=divider.divider.d_pipe[6](17) I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[6](16) I1=divider.divider.s_pipe[6](15) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[6](16) I1=divider.divider.s_pipe[6](15) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](16) D=divider.divider.s_pipe[7]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[6](16) I3=divider.divider.s_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](14) I3=divider.divider.d_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](14) I3=divider.divider.d_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[7](15) D=divider.divider.s_pipe[7]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[6](24) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](13) I2=divider.divider.d_pipe[6](14) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[6](13) I1=divider.divider.s_pipe[6](12) I2=divider.divider.s_pipe[6](11) I3=divider.divider.d_pipe[6](12) O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](13) I2=divider.divider.d_pipe[6](14) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[6](13) I1=divider.divider.s_pipe[6](12) I2=divider.divider.s_pipe[6](11) I3=divider.divider.d_pipe[6](12) O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[6](14) I2=divider.divider.s_pipe[6](13) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[6](14) I2=divider.divider.s_pipe[6](13) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](14) I3=divider.divider.d_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[6](23) O=divider.divider.s_pipe[7]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[6](19) I2=divider.divider.s_pipe[6](20) I3=divider.divider.s_pipe[6](24) O=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](22) I3=divider.divider.s_pipe[6](21) O=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[6](21) I1=divider.divider.s_pipe[6](22) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](24) D=divider.divider.s_pipe[8]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](23) D=divider.divider.s_pipe[8]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](14) D=divider.divider.s_pipe[8]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](13) I2=divider.divider.d_pipe[7](14) I3=divider.divider.s_pipe[8]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](13) D=divider.divider.s_pipe[8]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](12) I2=divider.divider.d_pipe[7](13) I3=divider.divider.s_pipe[8]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[7](12) I2=divider.divider.s_pipe[7](11) I3=divider.divider.s_pipe[7](24) O=divider.divider.s_pipe[8]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](12) D=divider.divider.s_pipe[8]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](11) I3=divider.divider.d_pipe[7](12) O=divider.divider.s_pipe[8]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](11) D=divider.divider.s_pipe[7](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](10) D=divider.divider.s_pipe[7](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](9) D=divider.divider.s_pipe[7](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](8) D=divider.divider.s_pipe[7](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[7](21) I2=divider.divider.s_pipe[8]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[7](22) O=divider.divider.s_pipe[8]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[7](21) O=divider.divider.s_pipe[8]_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](22) D=divider.divider.s_pipe[8]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[7](21) O=divider.divider.s_pipe[8]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](20) I3=divider.divider.s_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](21) D=divider.divider.s_pipe[8]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](20) I3=divider.divider.s_pipe[8]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7](24) I1=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011100001111
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](20) D=divider.divider.s_pipe[8]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[7](19) I1=divider.divider.s_pipe[7](18) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](19) D=divider.divider.s_pipe[8]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[7](24) I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](17) I3=divider.divider.d_pipe[7](18) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](17) I3=divider.divider.d_pipe[7](18) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[7](18) I3=divider.divider.d_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](18) I3=divider.divider.d_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](18) D=divider.divider.s_pipe[8]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[7](24) I3=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](16) I2=divider.divider.d_pipe[7](17) I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](16) I2=divider.divider.d_pipe[7](17) I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[7](17) I2=divider.divider.s_pipe[7](16) I3=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[7](17) I2=divider.divider.s_pipe[7](16) I3=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](17) I3=divider.divider.d_pipe[7](18) O=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](17) D=divider.divider.s_pipe[8]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](16) I2=divider.divider.d_pipe[7](17) I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[7](16) I1=divider.divider.s_pipe[7](15) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[7](16) I1=divider.divider.s_pipe[7](15) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](16) D=divider.divider.s_pipe[8]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[7](16) I3=divider.divider.s_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](14) I3=divider.divider.d_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](14) I3=divider.divider.d_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[8](15) D=divider.divider.s_pipe[8]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[7](24) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](13) I2=divider.divider.d_pipe[7](14) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[7](13) I1=divider.divider.s_pipe[7](12) I2=divider.divider.s_pipe[7](11) I3=divider.divider.d_pipe[7](12) O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](13) I2=divider.divider.d_pipe[7](14) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[7](13) I1=divider.divider.s_pipe[7](12) I2=divider.divider.s_pipe[7](11) I3=divider.divider.d_pipe[7](12) O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[7](14) I2=divider.divider.s_pipe[7](13) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[7](14) I2=divider.divider.s_pipe[7](13) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](14) I3=divider.divider.d_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[7](23) O=divider.divider.s_pipe[8]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[7](19) I2=divider.divider.s_pipe[7](20) I3=divider.divider.s_pipe[7](24) O=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](22) I3=divider.divider.s_pipe[7](21) O=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[7](21) I1=divider.divider.s_pipe[7](22) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](24) D=divider.divider.s_pipe[9]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](23) D=divider.divider.s_pipe[9]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](14) D=divider.divider.s_pipe[9]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](13) I2=divider.divider.d_pipe[8](14) I3=divider.divider.s_pipe[9]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](13) D=divider.divider.s_pipe[9]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](12) I2=divider.divider.d_pipe[8](13) I3=divider.divider.s_pipe[9]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[8](12) I2=divider.divider.s_pipe[8](11) I3=divider.divider.s_pipe[8](24) O=divider.divider.s_pipe[9]_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](12) D=divider.divider.s_pipe[9]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](11) I3=divider.divider.d_pipe[8](12) O=divider.divider.s_pipe[9]_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](11) D=divider.divider.s_pipe[8](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](10) D=divider.divider.s_pipe[8](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](9) D=divider.divider.s_pipe[8](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[8](21) I2=divider.divider.s_pipe[9]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[8](22) O=divider.divider.s_pipe[9]_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[8](21) O=divider.divider.s_pipe[9]_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](22) D=divider.divider.s_pipe[9]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[8](21) O=divider.divider.s_pipe[9]_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](20) I3=divider.divider.s_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](21) D=divider.divider.s_pipe[9]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](20) I3=divider.divider.s_pipe[9]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8](24) I1=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111011100001111
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](20) D=divider.divider.s_pipe[9]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.d_pipe[8](19) I1=divider.divider.s_pipe[8](18) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](19) D=divider.divider.s_pipe[9]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[8](24) I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110010100011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](17) I3=divider.divider.d_pipe[8](18) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](17) I3=divider.divider.d_pipe[8](18) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[8](18) I3=divider.divider.d_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](18) I3=divider.divider.d_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](18) D=divider.divider.s_pipe[9]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[8](24) I3=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](16) I2=divider.divider.d_pipe[8](17) I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](16) I2=divider.divider.d_pipe[8](17) I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[8](17) I2=divider.divider.s_pipe[8](16) I3=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[8](17) I2=divider.divider.s_pipe[8](16) I3=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](17) I3=divider.divider.d_pipe[8](18) O=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](17) D=divider.divider.s_pipe[9]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](16) I2=divider.divider.d_pipe[8](17) I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=divider.divider.d_pipe[8](16) I1=divider.divider.s_pipe[8](15) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[8](16) I1=divider.divider.s_pipe[8](15) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](16) D=divider.divider.s_pipe[9]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[8](16) I3=divider.divider.s_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](14) I3=divider.divider.d_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](14) I3=divider.divider.d_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=divider.divider.s_pipe[9](15) D=divider.divider.s_pipe[9]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[8](24) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010001101011100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](13) I2=divider.divider.d_pipe[8](14) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=divider.divider.d_pipe[8](13) I1=divider.divider.s_pipe[8](12) I2=divider.divider.s_pipe[8](11) I3=divider.divider.d_pipe[8](12) O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](13) I2=divider.divider.d_pipe[8](14) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.divider.d_pipe[8](13) I1=divider.divider.s_pipe[8](12) I2=divider.divider.s_pipe[8](11) I3=divider.divider.d_pipe[8](12) O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[8](14) I2=divider.divider.s_pipe[8](13) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[8](14) I2=divider.divider.s_pipe[8](13) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](14) I3=divider.divider.d_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[8](23) O=divider.divider.s_pipe[9]_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011111111000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[8](19) I2=divider.divider.s_pipe[8](20) I3=divider.divider.s_pipe[8](24) O=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](22) I3=divider.divider.s_pipe[8](21) O=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=divider.divider.s_pipe[8](21) I1=divider.divider.s_pipe[8](22) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=divider.divider.d(7) I1=divider.divider.s_pipe[0](18) I2=divider.id_LUT4_I1_O I3=divider.id_LUT4_I3_1_O O=divider.id_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=divider.divider.d(1) I1=divider.divider.s_pipe[0](12) I2=divider.divider.s_pipe[0](11) I3=divider.divider.d(0) O=divider.id_LUT4_I0_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=divider.id_LUT4_I2_2_O I1=divider.divider.d(5) I2=divider.divider.s_pipe[0](16) I3=divider.id_LUT4_I3_2_O O=divider.id_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=divider.divider.s_pipe[0](11) I1=divider.divider.d(0) I2=divider.divider.d(1) I3=divider.divider.s_pipe[0](12) O=divider.divider.s_pipe[1]_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101110110100
|
|
.subckt LUT4 I0=divider.id_LUT4_I1_O I1=divider.id_LUT4_I3_1_O I2=divider.divider.d(7) I3=divider.divider.s_pipe[0](18) O=divider.divider.s_pipe[1]_ff_CQZ_D(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=divider.id_LUT4_I2_2_O I1=divider.divider.s_pipe[0](16) I2=divider.divider.d(5) I3=divider.id_LUT4_I3_2_O O=divider.divider.s_pipe[1]_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111001110001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](15) I2=divider.divider.d(4) I3=divider.id_LUT4_I2_4_O O=divider.id_LUT4_I2_2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](16) I2=divider.divider.d(5) I3=divider.id_LUT4_I2_2_O O=divider.divider.s_pipe[1]_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](14) I2=divider.divider.d(3) I3=divider.id_LUT4_I2_6_O O=divider.id_LUT4_I2_4_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](15) I2=divider.divider.d(4) I3=divider.id_LUT4_I2_4_O O=divider.divider.s_pipe[1]_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](13) I2=divider.divider.d(2) I3=divider.id_LUT4_I0_1_O O=divider.id_LUT4_I2_6_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](14) I2=divider.divider.d(3) I3=divider.id_LUT4_I2_6_O O=divider.divider.s_pipe[1]_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](13) I2=divider.divider.d(2) I3=divider.id_LUT4_I0_1_O O=divider.divider.s_pipe[1]_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](11) I3=divider.divider.d(0) O=divider.divider.s_pipe[1]_ff_CQZ_D(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](17) I3=divider.divider.d(6) O=divider.id_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](17) I3=divider.divider.d(6) O=divider.id_LUT4_I3_2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=divider.divider.d(7) D=divider.d(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(6) D=divider.d(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(5) D=divider.d(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(4) D=divider.d(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(3) D=divider.d(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(2) D=divider.d(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(1) D=divider.d(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.d(0) D=divider.d(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](23) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](22) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](13) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](12) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](11) D=divider.iz_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.iz_ff_CQZ_13_D_LUT4_O_I3 I2=divider.z(11) I3=divider.z(10) O=divider.iz_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](10) D=divider.iz_ff_CQZ_13_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.z(10) I2=divider.z(11) I3=divider.iz_ff_CQZ_13_D_LUT4_O_I3 O=divider.iz_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.z(7) I1=divider.z(8) I2=divider.z(9) I3=divider.iz_ff_CQZ_16_D_LUT4_O_I3 O=divider.iz_ff_CQZ_13_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](9) D=divider.iz_ff_CQZ_14_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.z(9) I3=divider.iz_ff_CQZ_14_D_LUT4_O_I3 O=divider.iz_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.z(8) I1=divider.z(7) I2=divider.iz_ff_CQZ_16_D_LUT4_O_I3 I3=divider.z(11) O=divider.iz_ff_CQZ_14_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](8) D=divider.iz_ff_CQZ_15_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.iz_ff_CQZ_16_D_LUT4_O_I3 I1=divider.z(7) I2=divider.z(11) I3=divider.z(8) O=divider.iz_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](7) D=divider.iz_ff_CQZ_16_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.z(7) I2=divider.z(11) I3=divider.iz_ff_CQZ_16_D_LUT4_O_I3 O=divider.iz_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.z(4) I1=divider.z(5) I2=divider.z(6) I3=divider.iz_ff_CQZ_19_D_LUT4_O_I3 O=divider.iz_ff_CQZ_16_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](6) D=divider.iz_ff_CQZ_17_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.z(6) I3=divider.iz_ff_CQZ_17_D_LUT4_O_I3 O=divider.iz_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.z(5) I1=divider.z(4) I2=divider.iz_ff_CQZ_19_D_LUT4_O_I3 I3=divider.z(11) O=divider.iz_ff_CQZ_17_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](5) D=divider.iz_ff_CQZ_18_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.iz_ff_CQZ_19_D_LUT4_O_I3 I1=divider.z(4) I2=divider.z(11) I3=divider.z(5) O=divider.iz_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111010000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](4) D=divider.iz_ff_CQZ_19_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.z(4) I2=divider.z(11) I3=divider.iz_ff_CQZ_19_D_LUT4_O_I3 O=divider.iz_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.z(1) I1=divider.z(2) I2=divider.z(3) I3=divider.z(0) O=divider.iz_ff_CQZ_19_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](21) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](3) D=divider.iz_ff_CQZ_20_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.z(3) I3=divider.iz_ff_CQZ_20_D_LUT4_O_I3 O=divider.iz_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.z(2) I1=divider.z(0) I2=divider.z(1) I3=divider.z(11) O=divider.iz_ff_CQZ_20_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](2) D=divider.iz_ff_CQZ_21_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.z(1) I1=divider.z(0) I2=divider.z(11) I3=divider.z(2) O=divider.iz_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111100000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](1) D=divider.iz_ff_CQZ_22_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.z(1) I2=divider.z(0) I3=divider.z(11) O=divider.iz_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](0) D=divider.z(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](20) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](19) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](18) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](17) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](16) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](15) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.divider.s_pipe[0](14) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.q(12) D=divider.q_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.q(11) D=divider.q_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.q(2) D=divider.q_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.divider.q(1) I1=divider.divider.q(0) I2=divider.spipe(13) I3=divider.divider.q(2) O=divider.q_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111111100000
|
|
.subckt ff CQZ=divider.q(1) D=divider.q_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.q(1) I2=divider.divider.q(0) I3=divider.spipe(13) O=divider.q_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt ff CQZ=divider.q(0) D=divider.divider.q(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(11) I3=divider.q_ff_CQZ_D_LUT4_O_I3 O=divider.q_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=divider.q(10) D=divider.q_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.q_ff_CQZ_3_D_LUT4_O_I3 I1=divider.divider.q(9) I2=divider.spipe(13) I3=divider.divider.q(10) O=divider.q_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111010000
|
|
.subckt ff CQZ=divider.q(9) D=divider.q_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(9) I3=divider.q_ff_CQZ_3_D_LUT4_O_I3 O=divider.q_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=divider.divider.q(8) I1=divider.divider.q(7) I2=divider.q_ff_CQZ_5_D_LUT4_O_I3 I3=divider.spipe(13) O=divider.q_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000011111111
|
|
.subckt ff CQZ=divider.q(8) D=divider.q_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.q_ff_CQZ_5_D_LUT4_O_I3 I1=divider.divider.q(7) I2=divider.spipe(13) I3=divider.divider.q(8) O=divider.q_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111010000
|
|
.subckt ff CQZ=divider.q(7) D=divider.q_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.q(7) I2=divider.spipe(13) I3=divider.q_ff_CQZ_5_D_LUT4_O_I3 O=divider.q_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.divider.q(4) I1=divider.divider.q(5) I2=divider.divider.q(6) I3=divider.q_ff_CQZ_8_D_LUT4_O_I3 O=divider.q_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt ff CQZ=divider.q(6) D=divider.q_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(6) I3=divider.q_ff_CQZ_6_D_LUT4_O_I3 O=divider.q_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.divider.q(5) I1=divider.divider.q(4) I2=divider.q_ff_CQZ_8_D_LUT4_O_I3 I3=divider.spipe(13) O=divider.q_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt ff CQZ=divider.q(5) D=divider.q_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.q_ff_CQZ_8_D_LUT4_O_I3 I1=divider.divider.q(4) I2=divider.spipe(13) I3=divider.divider.q(5) O=divider.q_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010111111010000
|
|
.subckt ff CQZ=divider.q(4) D=divider.q_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.divider.q(4) I2=divider.spipe(13) I3=divider.q_ff_CQZ_8_D_LUT4_O_I3 O=divider.q_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.divider.q(1) I1=divider.divider.q(2) I2=divider.divider.q(3) I3=divider.divider.q(0) O=divider.q_ff_CQZ_8_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=divider.q(3) D=divider.q_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(3) I3=divider.q_ff_CQZ_9_D_LUT4_O_I3 O=divider.q_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.divider.q(2) I1=divider.divider.q(0) I2=divider.divider.q(1) I3=divider.spipe(13) O=divider.q_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.spipe(13) I2=divider.divider.q(11) I3=divider.q_ff_CQZ_D_LUT4_O_I3 O=divider.q_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010000
|
|
.subckt LUT4 I0=divider.divider.q(10) I1=divider.divider.q(9) I2=divider.q_ff_CQZ_3_D_LUT4_O_I3 I3=divider.spipe(13) O=divider.q_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000011111111
|
|
.subckt ff CQZ=divider.spipe(13) D=divider.spipe(12) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(12) D=divider.spipe(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(3) D=divider.spipe(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(2) D=divider.spipe(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(1) D=divider.spipe(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(0) D=divider.z(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(11) D=divider.spipe(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(10) D=divider.spipe(9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(9) D=divider.spipe(8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(8) D=divider.spipe(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(7) D=divider.spipe(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(6) D=divider.spipe(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(5) D=divider.spipe(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=divider.spipe(4) D=divider.spipe(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=dep(15) D=dep(14) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt LUT4 I0=dstrb_LUT4_I3_I2 I1=$iopadmap$qnt_cnt(4) I2=$iopadmap$dstrb I3=$iopadmap$qnt_cnt(5) O=dstrb_LUT4_I3_O(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=$iopadmap$dstrb I3=dstrb_LUT4_I2_1_I3 O=dstrb_LUT4_I3_O(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=$iopadmap$qnt_cnt(0) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$qnt_cnt(2) I3=$iopadmap$qnt_cnt(3) O=dstrb_LUT4_I2_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=$iopadmap$qnt_cnt(0) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$dstrb I3=$iopadmap$qnt_cnt(2) O=dstrb_LUT4_I3_O(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=$iopadmap$dstrb I3=$iopadmap$qnt_cnt(0) O=dstrb_LUT4_I3_O(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=$iopadmap$dstrb I3=divider.divider.ena O=qnt_cnt_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=divider.d(10) I1=$iopadmap$qnt_cnt(4) I2=dstrb_LUT4_I3_I2 I3=$iopadmap$dstrb O=dstrb_LUT4_I3_O(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=divider.d(10) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$qnt_cnt(0) I3=$iopadmap$dstrb O=dstrb_LUT4_I3_O(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=$iopadmap$qnt_cnt(0) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$qnt_cnt(2) I3=$iopadmap$qnt_cnt(3) O=dstrb_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=$iopadmap$qnt_cnt(5) D=dstrb_LUT4_I3_O(5) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt ff CQZ=$iopadmap$qnt_cnt(4) D=dstrb_LUT4_I3_O(4) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt ff CQZ=$iopadmap$qnt_cnt(3) D=dstrb_LUT4_I3_O(3) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt ff CQZ=$iopadmap$qnt_cnt(2) D=dstrb_LUT4_I3_O(2) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt ff CQZ=$iopadmap$qnt_cnt(1) D=dstrb_LUT4_I3_O(1) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt ff CQZ=$iopadmap$qnt_cnt(0) D=dstrb_LUT4_I3_O(0) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
|
|
.subckt ff CQZ=rq(11) D=rq_ff_CQZ_D(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(10) D=rq_ff_CQZ_D(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(1) D=rq_ff_CQZ_D(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(9) D=rq_ff_CQZ_D(9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(8) D=rq_ff_CQZ_D(8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(7) D=rq_ff_CQZ_D(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(6) D=rq_ff_CQZ_D(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(5) D=rq_ff_CQZ_D(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(4) D=rq_ff_CQZ_D(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(3) D=rq_ff_CQZ_D(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=rq(2) D=rq_ff_CQZ_D(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=divider.q(12) I1=rq_ff_CQZ_D_LUT4_O_I1 I2=rq_ff_CQZ_D_LUT4_O_I2 I3=divider.q(11) O=rq_ff_CQZ_D(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111101000000
|
|
.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O I1=rq_ff_CQZ_D_LUT4_O_I2 I2=divider.q(9) I3=divider.q(10) O=rq_ff_CQZ_D(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111110000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.q(1) I2=divider.q(0) I3=divider.q(12) O=rq_ff_CQZ_D(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.q(9) I2=rq_ff_CQZ_D_LUT4_O_I2 I3=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O O=rq_ff_CQZ_D(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.q(8) I3=rq_ff_CQZ_D_LUT4_O_3_I3 O=rq_ff_CQZ_D(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O I1=divider.q(5) I2=divider.q(6) I3=divider.q(7) O=rq_ff_CQZ_D_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O I1=divider.q(5) I2=divider.q(6) I3=divider.q(7) O=rq_ff_CQZ_D(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111110000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.q(6) I2=divider.q(5) I3=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O O=rq_ff_CQZ_D(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.q(5) I3=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O O=rq_ff_CQZ_D(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.q(4) I2=divider.q(3) I3=rq_ff_CQZ_D_LUT4_O_8_I3 O=rq_ff_CQZ_D(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.q(3) I3=rq_ff_CQZ_D_LUT4_O_8_I3 O=rq_ff_CQZ_D(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.q(4) I2=divider.q(3) I3=rq_ff_CQZ_D_LUT4_O_8_I3 O=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=divider.q(12) I1=divider.q(1) I2=divider.q(2) I3=divider.q(0) O=rq_ff_CQZ_D_LUT4_O_8_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=divider.q(12) I1=divider.q(1) I2=divider.q(0) I3=divider.q(2) O=rq_ff_CQZ_D(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111101000000
|
|
.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=divider.q(4) I2=divider.q(9) I3=divider.q(10) O=rq_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.q(3) I1=divider.q(2) I2=divider.q(1) I3=divider.q(0) O=rq_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.q(5) I1=divider.q(6) I2=divider.q(7) I3=divider.q(8) O=rq_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=$iopadmap$rst O=rst_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.end
|