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riscv
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SOFA
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https://github.com/lnis-uofu/SOFA.git
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c264ee0ddd
SOFA
/
TESTBENCH
/
k4_N8_caravel_io_FPGA_12x12...
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tangxifan
501c2799ed
[Testbench] Rename testbench to be consistent with post-PnR netlist path change
2020-12-14 20:27:22 -07:00
..
postpnr
/verilog_testbench
[Testbench] Rename testbench to be consistent with post-PnR netlist path change
2020-12-14 20:27:22 -07:00
prepnr
/verilog_testbench
[Testbench] Add configuration chain test benches for pre- and post- pnr simulation
2020-11-18 15:58:00 -07:00