mirror of https://github.com/lnis-uofu/SOFA.git
24836 lines
3.0 MiB
24836 lines
3.0 MiB
# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
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.model sdc_controller
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.inputs wb_clk_i wb_rst_i wb_dat_i(0) wb_dat_i(1) wb_dat_i(2) wb_dat_i(3) wb_dat_i(4) wb_dat_i(5) wb_dat_i(6) wb_dat_i(7) wb_dat_i(8) wb_dat_i(9) wb_dat_i(10) wb_dat_i(11) wb_dat_i(12) wb_dat_i(13) wb_dat_i(14) wb_dat_i(15) wb_dat_i(16) wb_dat_i(17) wb_dat_i(18) wb_dat_i(19) wb_dat_i(20) wb_dat_i(21) wb_dat_i(22) wb_dat_i(23) wb_dat_i(24) wb_dat_i(25) wb_dat_i(26) wb_dat_i(27) wb_dat_i(28) wb_dat_i(29) wb_dat_i(30) wb_dat_i(31) wb_adr_i(0) wb_adr_i(1) wb_adr_i(2) wb_adr_i(3) wb_adr_i(4) wb_adr_i(5) wb_adr_i(6) wb_adr_i(7) wb_sel_i(0) wb_sel_i(1) wb_sel_i(2) wb_sel_i(3) wb_we_i wb_cyc_i wb_stb_i m_wb_dat_i(0) m_wb_dat_i(1) m_wb_dat_i(2) m_wb_dat_i(3) m_wb_dat_i(4) m_wb_dat_i(5) m_wb_dat_i(6) m_wb_dat_i(7) m_wb_dat_i(8) m_wb_dat_i(9) m_wb_dat_i(10) m_wb_dat_i(11) m_wb_dat_i(12) m_wb_dat_i(13) m_wb_dat_i(14) m_wb_dat_i(15) m_wb_dat_i(16) m_wb_dat_i(17) m_wb_dat_i(18) m_wb_dat_i(19) m_wb_dat_i(20) m_wb_dat_i(21) m_wb_dat_i(22) m_wb_dat_i(23) m_wb_dat_i(24) m_wb_dat_i(25) m_wb_dat_i(26) m_wb_dat_i(27) m_wb_dat_i(28) m_wb_dat_i(29) m_wb_dat_i(30) m_wb_dat_i(31) m_wb_ack_i sd_cmd_dat_i sd_dat_dat_i(0) sd_dat_dat_i(1) sd_dat_dat_i(2) sd_dat_dat_i(3) sd_clk_i_pad
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.outputs wb_dat_o(0) wb_dat_o(1) wb_dat_o(2) wb_dat_o(3) wb_dat_o(4) wb_dat_o(5) wb_dat_o(6) wb_dat_o(7) wb_dat_o(8) wb_dat_o(9) wb_dat_o(10) wb_dat_o(11) wb_dat_o(12) wb_dat_o(13) wb_dat_o(14) wb_dat_o(15) wb_dat_o(16) wb_dat_o(17) wb_dat_o(18) wb_dat_o(19) wb_dat_o(20) wb_dat_o(21) wb_dat_o(22) wb_dat_o(23) wb_dat_o(24) wb_dat_o(25) wb_dat_o(26) wb_dat_o(27) wb_dat_o(28) wb_dat_o(29) wb_dat_o(30) wb_dat_o(31) wb_ack_o m_wb_dat_o(0) m_wb_dat_o(1) m_wb_dat_o(2) m_wb_dat_o(3) m_wb_dat_o(4) m_wb_dat_o(5) m_wb_dat_o(6) m_wb_dat_o(7) m_wb_dat_o(8) m_wb_dat_o(9) m_wb_dat_o(10) m_wb_dat_o(11) m_wb_dat_o(12) m_wb_dat_o(13) m_wb_dat_o(14) m_wb_dat_o(15) m_wb_dat_o(16) m_wb_dat_o(17) m_wb_dat_o(18) m_wb_dat_o(19) m_wb_dat_o(20) m_wb_dat_o(21) m_wb_dat_o(22) m_wb_dat_o(23) m_wb_dat_o(24) m_wb_dat_o(25) m_wb_dat_o(26) m_wb_dat_o(27) m_wb_dat_o(28) m_wb_dat_o(29) m_wb_dat_o(30) m_wb_dat_o(31) m_wb_adr_o(0) m_wb_adr_o(1) m_wb_adr_o(2) m_wb_adr_o(3) m_wb_adr_o(4) m_wb_adr_o(5) m_wb_adr_o(6) m_wb_adr_o(7) m_wb_adr_o(8) m_wb_adr_o(9) m_wb_adr_o(10) m_wb_adr_o(11) m_wb_adr_o(12) m_wb_adr_o(13) m_wb_adr_o(14) m_wb_adr_o(15) m_wb_adr_o(16) m_wb_adr_o(17) m_wb_adr_o(18) m_wb_adr_o(19) m_wb_adr_o(20) m_wb_adr_o(21) m_wb_adr_o(22) m_wb_adr_o(23) m_wb_adr_o(24) m_wb_adr_o(25) m_wb_adr_o(26) m_wb_adr_o(27) m_wb_adr_o(28) m_wb_adr_o(29) m_wb_adr_o(30) m_wb_adr_o(31) m_wb_sel_o(0) m_wb_sel_o(1) m_wb_sel_o(2) m_wb_sel_o(3) m_wb_we_o m_wb_cyc_o m_wb_stb_o m_wb_cti_o(0) m_wb_cti_o(1) m_wb_cti_o(2) m_wb_bte_o(0) m_wb_bte_o(1) sd_cmd_out_o sd_cmd_oe_o sd_dat_out_o(0) sd_dat_out_o(1) sd_dat_out_o(2) sd_dat_out_o(3) sd_dat_oe_o sd_clk_o_pad int_cmd int_data
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.names $false
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.names $true
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1
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.names $undef
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.subckt logic_1 a=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe
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.subckt logic_0 a=sd_data_serial_host0.busy
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.subckt out_buff A=$iopadmap$int_cmd Q=int_cmd
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=$iopadmap$int_data Q=int_data
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt in_buff A=m_wb_ack_i Q=sd_fifo_filler0.wbm_ack_i
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(0) Q=m_wb_adr_o(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(1) Q=m_wb_adr_o(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(10) Q=m_wb_adr_o(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(11) Q=m_wb_adr_o(11)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(12) Q=m_wb_adr_o(12)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(13) Q=m_wb_adr_o(13)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(14) Q=m_wb_adr_o(14)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(15) Q=m_wb_adr_o(15)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(16) Q=m_wb_adr_o(16)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(17) Q=m_wb_adr_o(17)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(18) Q=m_wb_adr_o(18)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(19) Q=m_wb_adr_o(19)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(2) Q=m_wb_adr_o(2)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(20) Q=m_wb_adr_o(20)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(21) Q=m_wb_adr_o(21)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(22) Q=m_wb_adr_o(22)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(23) Q=m_wb_adr_o(23)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(24) Q=m_wb_adr_o(24)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(25) Q=m_wb_adr_o(25)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(26) Q=m_wb_adr_o(26)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(27) Q=m_wb_adr_o(27)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(28) Q=m_wb_adr_o(28)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(29) Q=m_wb_adr_o(29)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(3) Q=m_wb_adr_o(3)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(30) Q=m_wb_adr_o(30)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(31) Q=m_wb_adr_o(31)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(4) Q=m_wb_adr_o(4)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(5) Q=m_wb_adr_o(5)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(6) Q=m_wb_adr_o(6)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(7) Q=m_wb_adr_o(7)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(8) Q=m_wb_adr_o(8)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(9) Q=m_wb_adr_o(9)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_bte_o(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_bte_o(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_cti_o(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_cti_o(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_cti_o(2)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt out_buff A=sd_fifo_filler0.wbm_cyc_o Q=m_wb_cyc_o
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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.subckt in_buff A=m_wb_dat_i(0) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(0)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(1) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(1)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(10) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(10)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(11) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(11)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(12) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(12)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(13) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(13)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(14) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(14)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(15) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(15)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(16) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(16)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.subckt in_buff A=m_wb_dat_i(17) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(17)
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
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|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
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|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
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|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
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|
|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
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|
|
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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|
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|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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|
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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|
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|
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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|
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
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|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(3) Q=wb_dat_o(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(30) Q=wb_dat_o(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(31) Q=wb_dat_o(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(4) Q=wb_dat_o(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(5) Q=wb_dat_o(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(6) Q=wb_dat_o(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(7) Q=wb_dat_o(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(8) Q=wb_dat_o(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt out_buff A=sd_controller_wb0.wb_dat_o(9) Q=wb_dat_o(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
|
|
.subckt in_buff A=wb_rst_i Q=argument_reg_cross.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
.subckt in_buff A=wb_stb_i Q=sd_controller_wb0.wb_stb_i
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
.subckt in_buff A=wb_we_i Q=sd_controller_wb0.wb_we_i
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](31) D=argument_reg_cross.in(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](30) D=argument_reg_cross.in(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](21) D=argument_reg_cross.in(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](20) D=argument_reg_cross.in(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](19) D=argument_reg_cross.in(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](18) D=argument_reg_cross.in(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](17) D=argument_reg_cross.in(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](16) D=argument_reg_cross.in(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](15) D=argument_reg_cross.in(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](14) D=argument_reg_cross.in(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](13) D=argument_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](12) D=argument_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](29) D=argument_reg_cross.in(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](11) D=argument_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](10) D=argument_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](9) D=argument_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](8) D=argument_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](7) D=argument_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](6) D=argument_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](5) D=argument_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](4) D=argument_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](3) D=argument_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](2) D=argument_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](28) D=argument_reg_cross.in(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](1) D=argument_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](0) D=argument_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](27) D=argument_reg_cross.in(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](26) D=argument_reg_cross.in(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](25) D=argument_reg_cross.in(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](24) D=argument_reg_cross.in(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](23) D=argument_reg_cross.in(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](22) D=argument_reg_cross.in(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(31) D=argument_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(30) D=argument_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(21) D=argument_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(20) D=argument_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(19) D=argument_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(18) D=argument_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(17) D=argument_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(16) D=argument_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(15) D=argument_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(14) D=argument_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(13) D=argument_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(12) D=argument_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(29) D=argument_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(11) D=argument_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(10) D=argument_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(9) D=argument_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(8) D=argument_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(7) D=argument_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(6) D=argument_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(5) D=argument_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(4) D=argument_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(3) D=argument_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(2) D=argument_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(28) D=argument_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(1) D=argument_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(0) D=argument_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(27) D=argument_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(26) D=argument_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(25) D=argument_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(24) D=argument_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(23) D=argument_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=argument_reg_cross.out(22) D=argument_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](15) D=block_count_reg_cross.in(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](14) D=block_count_reg_cross.in(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](5) D=block_count_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](4) D=block_count_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](3) D=block_count_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](2) D=block_count_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](1) D=block_count_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](0) D=block_count_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](13) D=block_count_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](12) D=block_count_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](11) D=block_count_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](10) D=block_count_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](9) D=block_count_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](8) D=block_count_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](7) D=block_count_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](6) D=block_count_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(15) D=block_count_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(14) D=block_count_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(5) D=block_count_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(4) D=block_count_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(3) D=block_count_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(2) D=block_count_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(1) D=block_count_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(0) D=block_count_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(13) D=block_count_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(12) D=block_count_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(11) D=block_count_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(10) D=block_count_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(9) D=block_count_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(8) D=block_count_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(7) D=block_count_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_count_reg_cross.out(6) D=block_count_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](11) D=block_size_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](10) D=block_size_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](1) D=block_size_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](0) D=block_size_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](9) D=block_size_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](8) D=block_size_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](7) D=block_size_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](6) D=block_size_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](5) D=block_size_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](4) D=block_size_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](3) D=block_size_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](2) D=block_size_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(11) D=block_size_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(10) D=block_size_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(1) D=block_size_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(0) D=block_size_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(9) D=block_size_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(8) D=block_size_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(7) D=block_size_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(6) D=block_size_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(5) D=block_size_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(4) D=block_size_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(3) D=block_size_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=block_size_reg_cross.out(2) D=block_size_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(7) D=clock_divider0.ClockDiv_ff_CQZ_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(6) D=clock_divider0.ClockDiv_ff_CQZ_1_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(6) I2=clock_divider0.ClockDiv_ff_CQZ_D_LUT4_O_I0 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(5) D=clock_divider0.ClockDiv_ff_CQZ_2_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2 I1=clock_divider0.ClockDiv(4) I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN I3=clock_divider0.ClockDiv(5) O=clock_divider0.ClockDiv_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(4) D=clock_divider0.ClockDiv_ff_CQZ_3_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(4) I2=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.ClockDiv(1) I2=clock_divider0.ClockDiv(2) I3=clock_divider0.ClockDiv(3) O=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(3) D=clock_divider0.ClockDiv_ff_CQZ_4_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=clock_divider0.ClockDiv_ff_CQZ_4_D_LUT4_O_I2 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.ClockDiv(1) I2=clock_divider0.ClockDiv(2) I3=clock_divider0.ClockDiv(3) O=clock_divider0.ClockDiv_ff_CQZ_4_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(2) D=clock_divider0.ClockDiv_ff_CQZ_5_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.ClockDiv(1) I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN I3=clock_divider0.ClockDiv(2) O=clock_divider0.ClockDiv_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(1) D=clock_divider0.ClockDiv_ff_CQZ_6_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(1) I2=clock_divider0.ClockDiv(0) I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=clock_divider0.ClockDiv(0) D=clock_divider0.ClockDiv_ff_CQZ_7_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=clock_divider0.ClockDiv(0) I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv_ff_CQZ_D_LUT4_O_I0 I1=clock_divider0.ClockDiv(6) I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN I3=clock_divider0.ClockDiv(7) O=clock_divider0.ClockDiv_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(5) I2=clock_divider0.ClockDiv(4) I3=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2 O=clock_divider0.ClockDiv_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=argument_reg_cross.clk_b D=clock_divider0.SD_CLK_O_ff_CQZ_D QCK=clock_divider0.CLK QEN=clock_divider0.SD_CLK_O_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.busy I3=argument_reg_cross.clk_b O=clock_divider0.SD_CLK_O_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt LUT4 I0=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I0 I1=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I1 I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I2 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I3 O=clock_divider0.SD_CLK_O_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(1) I1=clock_divider0.DIVIDER(1) I2=clock_divider0.ClockDiv(6) I3=clock_divider0.DIVIDER(6) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(4) I1=clock_divider0.DIVIDER(4) I2=clock_divider0.ClockDiv(5) I3=clock_divider0.DIVIDER(5) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.DIVIDER(0) I2=clock_divider0.ClockDiv(3) I3=clock_divider0.DIVIDER(3) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=clock_divider0.ClockDiv(2) I1=clock_divider0.DIVIDER(2) I2=clock_divider0.ClockDiv(7) I3=clock_divider0.DIVIDER(7) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](7) D=clock_divider_reg_cross.in(7) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](6) D=clock_divider_reg_cross.in(6) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](5) D=clock_divider_reg_cross.in(5) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](4) D=clock_divider_reg_cross.in(4) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](3) D=clock_divider_reg_cross.in(3) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](2) D=clock_divider_reg_cross.in(2) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](1) D=clock_divider_reg_cross.in(1) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](0) D=clock_divider_reg_cross.in(0) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(7) D=clock_divider_reg_cross.sync_clk_b[0](7) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(6) D=clock_divider_reg_cross.sync_clk_b[0](6) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(5) D=clock_divider_reg_cross.sync_clk_b[0](5) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(4) D=clock_divider_reg_cross.sync_clk_b[0](4) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(3) D=clock_divider_reg_cross.sync_clk_b[0](3) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(2) D=clock_divider_reg_cross.sync_clk_b[0](2) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(1) D=clock_divider_reg_cross.sync_clk_b[0](1) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=clock_divider0.DIVIDER(0) D=clock_divider_reg_cross.sync_clk_b[0](0) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=cmd_int_rst_cross.sync_clk_b(1) I3=cmd_int_rst_cross.sync_clk_b(2) O=sd_cmd_master0.int_status_reg_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=cmd_int_rst_cross.sync_clk_b(2) D=cmd_int_rst_cross.sync_clk_b(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_rst_cross.sync_clk_b(1) D=cmd_int_rst_cross.sync_clk_b(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_rst_cross.sync_clk_b(0) D=cmd_int_rst_cross.toggle_clk_a QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_int_rst_cross.toggle_clk_a I2=cmd_int_rst_edge.sig_reg(0) I3=cmd_int_rst_edge.sig_reg(1) O=cmd_int_rst_cross.toggle_clk_a_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt ff CQZ=cmd_int_rst_cross.toggle_clk_a D=cmd_int_rst_cross.toggle_clk_a_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:57.1-63.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_rst_edge.sig_reg(1) D=cmd_int_rst_edge.sig_reg(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:381.13-381.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_rst_edge.sig_reg(0) D=cmd_int_rst_edge.sig QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:381.13-381.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(4) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(3) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(2) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(1) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(0) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](4) D=cmd_int_status_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](3) D=cmd_int_status_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](2) D=cmd_int_status_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](1) D=cmd_int_status_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](0) D=cmd_int_status_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.out(4) D=cmd_int_status_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.out(3) D=cmd_int_status_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.out(2) D=cmd_int_status_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.out(1) D=cmd_int_status_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_int_status_reg_cross.out(0) D=cmd_int_status_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(6) D=cmd_serial_host0.CRC_7.CRC(5) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(5) D=cmd_serial_host0.CRC_7.CRC(4) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(4) D=cmd_serial_host0.CRC_7.CRC(3) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(3) D=cmd_serial_host0.CRC_7.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(2) D=cmd_serial_host0.CRC_7.CRC(1) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(1) D=cmd_serial_host0.CRC_7.CRC(0) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(0) D=cmd_serial_host0.CRC_7.inv QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.CRC_7.CRC(2) I3=cmd_serial_host0.CRC_7.inv O=cmd_serial_host0.CRC_7.CRC_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.CRC_7.BITVAL I3=cmd_serial_host0.CRC_7.CRC(6) O=cmd_serial_host0.CRC_7.inv
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(39) D=cmd(39) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(38) D=cmd(38) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(29) D=cmd(29) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(28) D=cmd(28) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(27) D=cmd(27) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(26) D=cmd(26) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(25) D=cmd(25) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(24) D=cmd(24) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(23) D=cmd(23) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(22) D=cmd(22) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(21) D=cmd(21) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(20) D=cmd(20) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(37) D=cmd(37) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(19) D=cmd(19) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(18) D=cmd(18) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(17) D=cmd(17) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(16) D=cmd(16) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(15) D=cmd(15) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(14) D=cmd(14) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(13) D=cmd(13) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(12) D=cmd(12) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(11) D=cmd(11) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(10) D=cmd(10) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(36) D=cmd(36) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(9) D=cmd(9) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(8) D=cmd(8) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(7) D=cmd(7) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(6) D=cmd(6) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(5) D=cmd(5) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(4) D=cmd(4) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(3) D=cmd(3) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(2) D=cmd(2) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(1) D=cmd(1) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(0) D=cmd(0) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(35) D=cmd(35) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(34) D=cmd(34) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(33) D=cmd(33) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(32) D=cmd(32) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(31) D=cmd(31) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_buff(30) D=cmd(30) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_dat_reg D=cmd_serial_host0.cmd_dat_i QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:119.1-120.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_oe_o D=cmd_serial_host0.cmd_oe_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=cmd_serial_host0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_oe_o_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.cmd_oe_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_O I2=cmd_serial_host0.next_state_LUT4_O_3_I2 I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.cmd_oe_o_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=cmd_serial_host0.cmd_out_o D=cmd_serial_host0.cmd_out_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=cmd_serial_host0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101011100001111
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111110011111010
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(23) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(15) I1=cmd_serial_host0.cmd_buff(31) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(7) I1=cmd_serial_host0.cmd_buff(39) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(5) I1=cmd_serial_host0.cmd_buff(37) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_buff(21) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(29) I3=cmd_serial_host0.cmd_buff(13) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(18) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(34) I3=cmd_serial_host0.cmd_buff(2) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(26) I3=cmd_serial_host0.cmd_buff(10) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(14) I1=cmd_serial_host0.cmd_buff(30) I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(22) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(38) I3=cmd_serial_host0.cmd_buff(6) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(19) I2=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(3) I1=cmd_serial_host0.cmd_buff(35) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(17) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(9) I1=cmd_serial_host0.cmd_buff(25) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(1) I1=cmd_serial_host0.cmd_buff(33) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(31) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter(19) I3=cmd_serial_host0.counter(17) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(18) I1=cmd_serial_host0.counter(16) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(24) I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(5) I1=cmd_serial_host0.CRC_7.CRC(6) I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(0) I1=cmd_serial_host0.CRC_7.CRC(4) I2=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=cmd_serial_host0.CRC_7.CRC(2) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(1) I1=cmd_serial_host0.CRC_7.CRC(3) I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN O=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.state(4) I2=cmd_serial_host0.state(6) I3=cmd_serial_host0.state(5) O=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt ff CQZ=cmd_serial_host0.counter(31) D=cmd_serial_host0.counter_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.counter(30) D=cmd_serial_host0.counter_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.counter(21) D=cmd_serial_host0.counter_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter_ff_CQZ_10_D_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.counter_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=cmd_serial_host0.counter(20) D=cmd_serial_host0.counter_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.counter_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(19) D=cmd_serial_host0.counter_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(18) D=cmd_serial_host0.counter_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_I2 I3=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(19) I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(17) D=cmd_serial_host0.counter_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(17) I2=cmd_serial_host0.counter_ff_CQZ_14_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.counter_ff_CQZ_14_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2 I1=cmd_serial_host0.counter(14) I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.counter_ff_CQZ_14_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(16) D=cmd_serial_host0.counter_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_16_D_LUT4_O_I2 I1=cmd_serial_host0.counter(15) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.counter_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(15) D=cmd_serial_host0.counter_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(15) I2=cmd_serial_host0.counter_ff_CQZ_16_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2 I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.counter_ff_CQZ_16_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(14) D=cmd_serial_host0.counter_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(14) I2=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.counter(9) O=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(11) I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(13) D=cmd_serial_host0.counter_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2 I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(13) O=cmd_serial_host0.counter_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(12) D=cmd_serial_host0.counter_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.counter_ff_CQZ_D_LUT4_O_I0 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(29) D=cmd_serial_host0.counter_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.counter(11) D=cmd_serial_host0.counter_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2 I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(11) O=cmd_serial_host0.counter_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(10) D=cmd_serial_host0.counter_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(9) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(9) D=cmd_serial_host0.counter_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(9) O=cmd_serial_host0.counter_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(8) D=cmd_serial_host0.counter_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(7) D=cmd_serial_host0.counter_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(7) I2=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2 I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000100000000111
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(13) I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=cmd_serial_host0.counter(22) I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111111111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(6) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(6) D=cmd_serial_host0.counter_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.counter_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(5) D=cmd_serial_host0.counter_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(4) D=cmd_serial_host0.counter_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(4) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(4) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(3) D=cmd_serial_host0.counter_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=cmd_serial_host0.counter(2) D=cmd_serial_host0.counter_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2 I1=cmd_serial_host0.counter(28) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(29) O=cmd_serial_host0.counter_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(28) D=cmd_serial_host0.counter_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.counter(1) D=cmd_serial_host0.counter_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(0) D=cmd_serial_host0.counter_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(28) I2=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(27) D=cmd_serial_host0.counter_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter_ff_CQZ_4_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.counter_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.counter_ff_CQZ_4_D_LUT4_O_I1 I3=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(24) I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.counter_ff_CQZ_4_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(26) D=cmd_serial_host0.counter_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_6_D_LUT4_O_I2 I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.counter_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(25) D=cmd_serial_host0.counter_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.counter_ff_CQZ_6_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_9_D_LUT4_O_I2 I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.counter_ff_CQZ_6_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(24) D=cmd_serial_host0.counter_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(23) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.counter_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt ff CQZ=cmd_serial_host0.counter(23) D=cmd_serial_host0.counter_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(23) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt ff CQZ=cmd_serial_host0.counter(22) D=cmd_serial_host0.counter_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.counter_ff_CQZ_9_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.counter_ff_CQZ_9_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(31) O=cmd_serial_host0.counter_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(29) I2=cmd_serial_host0.counter(28) I3=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.BITVAL D=cmd_serial_host0.crc_bit_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_bit_ff_CQZ_QEN QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(1) I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111100010001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(28) I3=cmd_serial_host0.cmd_buff(12) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(20) I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(36) I3=cmd_serial_host0.cmd_buff(4) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(4) I2=cmd_serial_host0.cmd_buff(24) I3=cmd_serial_host0.cmd_buff(8) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.cmd_buff(16) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(0) I1=cmd_serial_host0.cmd_buff(32) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(23) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(39) I3=cmd_serial_host0.cmd_buff(7) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(15) I1=cmd_serial_host0.cmd_buff(31) I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_bit_ff_CQZ_QEN_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O O=cmd_serial_host0.crc_bit_ff_CQZ_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.ENABLE D=cmd_serial_host0.crc_enable_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_enable_ff_CQZ_QEN QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_oe_o_ff_CQZ_D_LUT4_O_I1 I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(11) I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.resp_len(13) I3=cmd_serial_host0.resp_len(14) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(7) I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.resp_len(9) I3=cmd_serial_host0.resp_len(10) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(19) I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.resp_len(22) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(15) I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.resp_len(17) I3=cmd_serial_host0.resp_len(18) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.resp_len(6) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(27) I1=cmd_serial_host0.resp_len(28) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.resp_len(30) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(23) I1=cmd_serial_host0.resp_len(24) I2=cmd_serial_host0.resp_len(25) I3=cmd_serial_host0.resp_len(26) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(31) I1=cmd_serial_host0.resp_len(0) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.resp_len(2) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O I2=cmd_serial_host0.crc_rst_ff_CQZ_D I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.crc_enable_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111101011110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(4) I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(4) I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(14) I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(9) I1=cmd_serial_host0.counter(11) I2=cmd_serial_host0.counter(12) I3=cmd_serial_host0.counter(13) O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(6) D=cmd_serial_host0.crc_in_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(5) D=cmd_serial_host0.crc_in_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(5) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2 O=cmd_serial_host0.crc_in_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101011001100
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(4) D=cmd_serial_host0.crc_in_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(4) I2=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(3) D=cmd_serial_host0.crc_in_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(3) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101011001100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(1) I1=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001100010000100
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(2) D=cmd_serial_host0.crc_in_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(2) I2=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(1) D=cmd_serial_host0.crc_in_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(1) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101011001100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=cmd_serial_host0.resp_len(1) O=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000101100000
|
|
.subckt ff CQZ=cmd_serial_host0.crc_in(0) D=cmd_serial_host0.crc_in_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1 I2=cmd_serial_host0.crc_in(0) I3=cmd_serial_host0.cmd_dat_reg O=cmd_serial_host0.crc_in_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110011001010
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(2) I1=cmd_serial_host0.resp_len(2) I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(0) I1=cmd_serial_host0.resp_len(0) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(1) I2=cmd_serial_host0.resp_len(0) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(0) I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111001110001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101110111010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(3) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(2) I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.resp_len(3) I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100110110110010
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(7) I3=cmd_serial_host0.counter(7) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3 I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011100010000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101111110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_O I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(2) I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.resp_len(3) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011010001001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(6) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.resp_len(1) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100011000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(2) I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.resp_len(0) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(0) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.crc_ok_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.crc_ok D=cmd_serial_host0.crc_ok_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(0) I1=cmd_serial_host0.crc_in(0) I2=cmd_serial_host0.CRC_7.CRC(5) I3=cmd_serial_host0.crc_in(5) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(2) I1=cmd_serial_host0.crc_in(2) I2=cmd_serial_host0.CRC_7.CRC(6) I3=cmd_serial_host0.crc_in(6) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_in(4) I3=cmd_serial_host0.CRC_7.CRC(4) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(3) I1=cmd_serial_host0.crc_in(3) I2=cmd_serial_host0.crc_in(1) I3=cmd_serial_host0.CRC_7.CRC(1) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.resp_len(22) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001100111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(23) I3=cmd_serial_host0.resp_len(23) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101111110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0 I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011100010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(20) I2=cmd_serial_host0.resp_len(20) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.counter(19) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(20) I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101111110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(19) I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(19) I3=cmd_serial_host0.counter(18) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.resp_len(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(23) I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.counter(23) I3=cmd_serial_host0.counter(22) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(21) I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.counter(21) I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(20) I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101111010111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(21) I3=cmd_serial_host0.resp_len(21) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.counter(14) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001100111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.resp_len(15) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(13) I3=cmd_serial_host0.counter(13) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.resp_len(13) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(11) I3=cmd_serial_host0.counter(11) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(25) I3=cmd_serial_host0.resp_len(25) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(25) I1=cmd_serial_host0.resp_len(24) I2=cmd_serial_host0.counter(25) I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(24) I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.counter(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011100010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.resp_len(14) I2=cmd_serial_host0.counter(14) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011100010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(15) I1=cmd_serial_host0.resp_len(15) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101110110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I2=cmd_serial_host0.counter(16) I3=cmd_serial_host0.resp_len(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100011101110
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(15) I1=cmd_serial_host0.resp_len(15) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(17) I3=cmd_serial_host0.counter(17) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011100010000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0_LUT4_I0_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.counter(18) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(19) I3=cmd_serial_host0.resp_len(19) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.counter(22) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(26) I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(27) I1=cmd_serial_host0.resp_len(27) I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101110110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(24) I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0 I1=cmd_serial_host0.resp_len(24) I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011100010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(24) I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001011001101001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(25) I1=cmd_serial_host0.resp_len(25) I2=cmd_serial_host0.resp_len(26) I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110110000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(25) I1=cmd_serial_host0.resp_len(25) I2=cmd_serial_host0.resp_len(26) I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101110110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110100100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(17) I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(10) I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I3 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O_LUT4_I3_1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O_LUT4_I3_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010010000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(9) I3=cmd_serial_host0.counter(9) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101111010111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.resp_len(3) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110001
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(14) I1=cmd_serial_host0.resp_len(14) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(3) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(7) I1=cmd_serial_host0.resp_len(6) I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(5) I1=cmd_serial_host0.resp_len(5) I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(6) I3=cmd_serial_host0.resp_len(6) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 I2=cmd_serial_host0.resp_len(6) I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(6) I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I2=cmd_serial_host0.resp_len(6) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.resp_len(7) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(3) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(27) I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.counter(29) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111001100110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(30) I1=cmd_serial_host0.resp_len(30) I2=cmd_serial_host0.resp_len(31) I3=cmd_serial_host0.counter(31) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101110110100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100010011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(30) I3=cmd_serial_host0.resp_len(30) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.counter(27) I3=cmd_serial_host0.resp_len(27) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000100110010000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100110111010100
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(28) I3=cmd_serial_host0.resp_len(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.resp_len(29) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(29) I1=cmd_serial_host0.resp_len(28) I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101111010111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(31) I3=cmd_serial_host0.resp_len(31) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.resp_len(30) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(31) I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000100010
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111111111111
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(9) I3=cmd_serial_host0.resp_len(9) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(13) I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(15) I1=cmd_serial_host0.resp_len(14) I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(9) I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.counter(9) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(11) I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.resp_len(11) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(14) I3=cmd_serial_host0.resp_len(14) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(16) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.resp_len(17) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt ff CQZ=cmd_serial_host0.crc_ok_o D=cmd_serial_host0.crc_ok_LUT4_I2_O QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.CRC_7.CLEAR D=cmd_serial_host0.crc_rst_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=cmd_serial_host0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.crc_rst_ff_CQZ_D O=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O I3=cmd_serial_host0.crc_rst_ff_CQZ_D O=cmd_serial_host0.crc_rst_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt ff CQZ=cmd_serial_host0.finish_o D=cmd_serial_host0.finish_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_5_I3 I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.finish_o_ff_CQZ_D O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_5_I3 I3=cmd_serial_host0.finish_o_ff_CQZ_D O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_3_I2 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O O=cmd_serial_host0.crc_rst_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=cmd_serial_host0.state(4) I1=cmd_serial_host0.state(5) I2=cmd_serial_host0.state(6) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.finish_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.state(6) I1=cmd_serial_host0.state(4) I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.state(5) O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.state(5) I1=cmd_serial_host0.state(6) I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.state(4) O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=cmd_serial_host0.state(2) I3=cmd_serial_host0.state(3) O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=cmd_serial_host0.index_ok_o D=cmd_serial_host0.index_ok_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O I1=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.index_ok_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(34) I1=cmd_serial_host0.resp_buff(122) I2=cmd_serial_host0.cmd_buff(37) I3=cmd_serial_host0.resp_buff(125) O=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(33) I1=cmd_serial_host0.resp_buff(121) I2=cmd_serial_host0.cmd_buff(36) I3=cmd_serial_host0.resp_buff(124) O=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(32) I1=cmd_serial_host0.resp_buff(120) I2=cmd_serial_host0.cmd_buff(35) I3=cmd_serial_host0.resp_buff(123) O=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.with_response O=cmd_serial_host0.next_state(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(31) I1=cmd_serial_host0.next_state_LUT4_O_1_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.next_state(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(31) I3=cmd_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(30) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.next_state_LUT4_O_3_I2 O=cmd_serial_host0.next_state(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(30) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.counter(29) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100010001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(28) I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.counter(26) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100110111111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.resp_len(25) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.resp_len(24) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(25) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011100010001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(25) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.resp_len(24) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111110000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000011111111
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(21) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(17) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
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.param EQN "(I0*I1*I2*I3)"
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.param INIT 10000000
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|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.counter(20) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
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.param INIT 1110100011101110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
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.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
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.param INIT 10000111
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|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
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.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
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.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
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|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.counter(14) I3=cmd_serial_host0.resp_len(14) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
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.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
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|
.subckt LUT4 I0=cmd_serial_host0.counter(13) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_len(13) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
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.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
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|
.param INIT 0000000001111101
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|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
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.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
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|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.resp_len(11) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
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.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(10) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
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.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
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|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111101
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.resp_len(9) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(9) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(7) I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.resp_len(7) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101011
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.resp_len(8) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(6) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(3) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.resp_len(3) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.resp_len(5) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.resp_len(6) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(7) I2=cmd_serial_host0.resp_len(7) I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.resp_len(9) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(12) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.resp_len(15) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(11) I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.resp_len(11) I3=cmd_serial_host0.counter(11) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(13) I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.resp_len(15) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(16) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111101
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.resp_len(17) I3=cmd_serial_host0.counter(17) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.resp_len(17) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.counter(18) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010010000001
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=cmd_serial_host0.resp_len(19) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(21) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111101
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.counter(23) I3=cmd_serial_host0.resp_len(23) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_len(27) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.resp_len(25) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=cmd_serial_host0.resp_len(29) I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110100100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010001000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(27) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(30) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.resp_len(31) I3=cmd_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.counter(31) I3=cmd_serial_host0.next_state_LUT4_O_1_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I1 I2=cmd_serial_host0.next_state_LUT4_O_3_I2 I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.next_state(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=cmd_serial_host0.state(2) I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=cmd_serial_host0.state(3) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.state(3) I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 I3=cmd_serial_host0.state(2) O=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.state(1) I3=cmd_serial_host0.state(0) O=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_4_I1 I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.next_state(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_4_I1 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_4_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.state(0) I1=cmd_serial_host0.state(3) I2=cmd_serial_host0.state(2) I3=cmd_serial_host0.state(1) O=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.start_i I3=cmd_serial_host0.next_state_LUT4_O_5_I3 O=cmd_serial_host0.next_state(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_5_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_5_I3 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.state(3) I1=cmd_serial_host0.state(1) I2=cmd_serial_host0.state(2) I3=cmd_serial_host0.state(0) O=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1 I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O I3=cmd_serial_host0.next_state(1) O=cmd_serial_host0.next_state(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_6_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(31) I3=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(4) I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(125) D=cmd_serial_host0.resp_buff_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(124) D=cmd_serial_host0.resp_buff_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(115) D=cmd_serial_host0.resp_buff_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(25) D=cmd_serial_host0.resp_buff_ff_CQZ_100_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(25) I2=cmd_serial_host0.resp_buff_ff_CQZ_100_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_100_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_100_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(24) D=cmd_serial_host0.resp_buff_ff_CQZ_101_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(24) I3=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_101_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(23) D=cmd_serial_host0.resp_buff_ff_CQZ_102_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(23) I3=cmd_serial_host0.resp_buff_ff_CQZ_102_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_102_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(23) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_102_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(22) D=cmd_serial_host0.resp_buff_ff_CQZ_103_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(22) I2=cmd_serial_host0.resp_buff_ff_CQZ_103_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_103_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_103_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(21) D=cmd_serial_host0.resp_buff_ff_CQZ_104_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(21) I3=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_104_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(20) D=cmd_serial_host0.resp_buff_ff_CQZ_105_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(20) I2=cmd_serial_host0.resp_buff_ff_CQZ_105_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_105_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_105_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(19) D=cmd_serial_host0.resp_buff_ff_CQZ_106_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(19) I3=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_106_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(19) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(18) D=cmd_serial_host0.resp_buff_ff_CQZ_107_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(18) I2=cmd_serial_host0.resp_buff_ff_CQZ_107_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_107_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_107_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(17) D=cmd_serial_host0.resp_buff_ff_CQZ_108_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(17) I2=cmd_serial_host0.resp_buff_ff_CQZ_108_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_108_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_108_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(16) D=cmd_serial_host0.resp_buff_ff_CQZ_109_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(16) I3=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_109_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_buff(115) I3=cmd_serial_host0.resp_buff_ff_CQZ_10_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(115) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(114) D=cmd_serial_host0.resp_buff_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(15) D=cmd_serial_host0.resp_buff_ff_CQZ_110_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(15) I3=cmd_serial_host0.resp_buff_ff_CQZ_110_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_110_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(15) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_110_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(14) D=cmd_serial_host0.resp_buff_ff_CQZ_111_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(14) I2=cmd_serial_host0.resp_buff_ff_CQZ_111_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_111_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_111_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(13) D=cmd_serial_host0.resp_buff_ff_CQZ_112_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(13) I3=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_112_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(12) D=cmd_serial_host0.resp_buff_ff_CQZ_113_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(12) I2=cmd_serial_host0.resp_buff_ff_CQZ_113_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_113_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_113_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(11) D=cmd_serial_host0.resp_buff_ff_CQZ_114_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(11) I3=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_114_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(11) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(10) D=cmd_serial_host0.resp_buff_ff_CQZ_115_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(10) I2=cmd_serial_host0.resp_buff_ff_CQZ_115_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_115_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_115_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(9) D=cmd_serial_host0.resp_buff_ff_CQZ_116_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(9) I2=cmd_serial_host0.resp_buff_ff_CQZ_116_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_116_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_116_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(8) D=cmd_serial_host0.resp_buff_ff_CQZ_117_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(8) I3=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_117_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(7) D=cmd_serial_host0.resp_buff_ff_CQZ_118_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(7) I3=cmd_serial_host0.resp_buff_ff_CQZ_118_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_118_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(7) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_118_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(6) D=cmd_serial_host0.resp_buff_ff_CQZ_119_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(6) I2=cmd_serial_host0.resp_buff_ff_CQZ_119_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_119_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_119_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(114) I2=cmd_serial_host0.resp_buff_ff_CQZ_11_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_11_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(113) D=cmd_serial_host0.resp_buff_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(5) D=cmd_serial_host0.resp_buff_ff_CQZ_120_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_120_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(4) D=cmd_serial_host0.resp_buff_ff_CQZ_121_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(4) I2=cmd_serial_host0.resp_buff_ff_CQZ_121_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_121_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_121_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(3) D=cmd_serial_host0.resp_buff_ff_CQZ_122_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_122_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(3) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(2) D=cmd_serial_host0.resp_buff_ff_CQZ_123_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(2) I2=cmd_serial_host0.resp_buff_ff_CQZ_123_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_123_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_123_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(1) D=cmd_serial_host0.resp_buff_ff_CQZ_124_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_124_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_124_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_124_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(0) D=cmd_serial_host0.resp_buff_ff_CQZ_125_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(0) I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(7) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(7) I2=cmd_serial_host0.resp_idx(8) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(5) I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx(31) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(30) I2=cmd_serial_host0.resp_idx(29) I3=cmd_serial_host0.resp_idx(28) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx(9) I1=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(15) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(17) I3=cmd_serial_host0.resp_idx(16) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(20) I2=cmd_serial_host0.resp_idx(19) I3=cmd_serial_host0.resp_idx(18) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx(8) I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_idx(6) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(113) I2=cmd_serial_host0.resp_buff_ff_CQZ_12_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_12_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(112) D=cmd_serial_host0.resp_buff_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff(112) I3=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_idx(3) O=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(112) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(111) D=cmd_serial_host0.resp_buff_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(111) I3=cmd_serial_host0.resp_buff_ff_CQZ_14_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(111) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_14_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(110) D=cmd_serial_host0.resp_buff_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(110) I2=cmd_serial_host0.resp_buff_ff_CQZ_15_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_15_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(109) D=cmd_serial_host0.resp_buff_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(109) I3=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(108) D=cmd_serial_host0.resp_buff_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(108) I2=cmd_serial_host0.resp_buff_ff_CQZ_17_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_17_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(107) D=cmd_serial_host0.resp_buff_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(107) I3=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(107) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(106) D=cmd_serial_host0.resp_buff_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(106) I2=cmd_serial_host0.resp_buff_ff_CQZ_19_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_19_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(124) O=cmd_serial_host0.resp_buff_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010001000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cmd_serial_host0.cmd_buff(19) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_buff(11) I1=cmd_serial_host0.cmd_buff(27) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(123) D=cmd_serial_host0.resp_buff_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(105) D=cmd_serial_host0.resp_buff_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(105) I2=cmd_serial_host0.resp_buff_ff_CQZ_20_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_20_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(104) D=cmd_serial_host0.resp_buff_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(104) I2=cmd_serial_host0.resp_buff_ff_CQZ_21_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_21_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(103) D=cmd_serial_host0.resp_buff_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff(103) I3=cmd_serial_host0.resp_buff_ff_CQZ_22_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(103) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_22_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(102) D=cmd_serial_host0.resp_buff_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(102) I2=cmd_serial_host0.resp_buff_ff_CQZ_23_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_23_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(101) D=cmd_serial_host0.resp_buff_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff(101) I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(3) I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(100) D=cmd_serial_host0.resp_buff_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(100) I2=cmd_serial_host0.resp_buff_ff_CQZ_25_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_25_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(99) D=cmd_serial_host0.resp_buff_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_buff(99) I3=cmd_serial_host0.resp_buff_ff_CQZ_26_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(99) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_26_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(98) D=cmd_serial_host0.resp_buff_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(98) I2=cmd_serial_host0.resp_buff_ff_CQZ_27_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_27_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(97) D=cmd_serial_host0.resp_buff_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(97) I2=cmd_serial_host0.resp_buff_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_28_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(96) D=cmd_serial_host0.resp_buff_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(96) I3=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(123) I3=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.cmd_dat_reg O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(123) I2=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(122) D=cmd_serial_host0.resp_buff_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(95) D=cmd_serial_host0.resp_buff_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(95) I3=cmd_serial_host0.resp_buff_ff_CQZ_30_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(95) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_30_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(94) D=cmd_serial_host0.resp_buff_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(94) I2=cmd_serial_host0.resp_buff_ff_CQZ_31_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_31_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(93) D=cmd_serial_host0.resp_buff_ff_CQZ_32_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(93) I3=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_32_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(92) D=cmd_serial_host0.resp_buff_ff_CQZ_33_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(92) I2=cmd_serial_host0.resp_buff_ff_CQZ_33_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_33_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_33_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(91) D=cmd_serial_host0.resp_buff_ff_CQZ_34_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(91) I3=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_34_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(91) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(90) D=cmd_serial_host0.resp_buff_ff_CQZ_35_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(90) I2=cmd_serial_host0.resp_buff_ff_CQZ_35_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_35_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_35_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(89) D=cmd_serial_host0.resp_buff_ff_CQZ_36_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(89) I2=cmd_serial_host0.resp_buff_ff_CQZ_36_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_36_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_36_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(88) D=cmd_serial_host0.resp_buff_ff_CQZ_37_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(88) I3=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_37_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(87) D=cmd_serial_host0.resp_buff_ff_CQZ_38_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(87) I3=cmd_serial_host0.resp_buff_ff_CQZ_38_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_38_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(87) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_38_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(86) D=cmd_serial_host0.resp_buff_ff_CQZ_39_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(86) I2=cmd_serial_host0.resp_buff_ff_CQZ_39_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_39_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_39_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(122) O=cmd_serial_host0.resp_buff_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.CRC_7.CRC(1) I3=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(0) I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(121) D=cmd_serial_host0.resp_buff_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(85) D=cmd_serial_host0.resp_buff_ff_CQZ_40_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(85) I3=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_40_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(84) D=cmd_serial_host0.resp_buff_ff_CQZ_41_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(84) I2=cmd_serial_host0.resp_buff_ff_CQZ_41_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_41_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_41_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(83) D=cmd_serial_host0.resp_buff_ff_CQZ_42_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(83) I3=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_42_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(83) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(82) D=cmd_serial_host0.resp_buff_ff_CQZ_43_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(82) I2=cmd_serial_host0.resp_buff_ff_CQZ_43_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_43_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_43_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(81) D=cmd_serial_host0.resp_buff_ff_CQZ_44_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(81) I2=cmd_serial_host0.resp_buff_ff_CQZ_44_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_44_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_44_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(80) D=cmd_serial_host0.resp_buff_ff_CQZ_45_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(80) I3=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_45_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(79) D=cmd_serial_host0.resp_buff_ff_CQZ_46_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(79) I3=cmd_serial_host0.resp_buff_ff_CQZ_46_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_46_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(79) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_46_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(78) D=cmd_serial_host0.resp_buff_ff_CQZ_47_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(78) I2=cmd_serial_host0.resp_buff_ff_CQZ_47_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_47_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_47_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(77) D=cmd_serial_host0.resp_buff_ff_CQZ_48_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(77) I3=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_48_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(76) D=cmd_serial_host0.resp_buff_ff_CQZ_49_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(76) I2=cmd_serial_host0.resp_buff_ff_CQZ_49_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_49_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_49_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(121) O=cmd_serial_host0.resp_buff_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(120) D=cmd_serial_host0.resp_buff_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(75) D=cmd_serial_host0.resp_buff_ff_CQZ_50_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(75) I3=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_50_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(75) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(74) D=cmd_serial_host0.resp_buff_ff_CQZ_51_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(74) I2=cmd_serial_host0.resp_buff_ff_CQZ_51_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_51_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_51_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(73) D=cmd_serial_host0.resp_buff_ff_CQZ_52_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(73) I2=cmd_serial_host0.resp_buff_ff_CQZ_52_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_52_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_52_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(72) D=cmd_serial_host0.resp_buff_ff_CQZ_53_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(72) I3=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_53_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(71) D=cmd_serial_host0.resp_buff_ff_CQZ_54_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(71) I3=cmd_serial_host0.resp_buff_ff_CQZ_54_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_54_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(71) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_54_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(70) D=cmd_serial_host0.resp_buff_ff_CQZ_55_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(70) I2=cmd_serial_host0.resp_buff_ff_CQZ_55_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_55_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_55_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(69) D=cmd_serial_host0.resp_buff_ff_CQZ_56_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(69) I3=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_56_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(68) D=cmd_serial_host0.resp_buff_ff_CQZ_57_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(68) I2=cmd_serial_host0.resp_buff_ff_CQZ_57_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_57_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_57_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(67) D=cmd_serial_host0.resp_buff_ff_CQZ_58_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(67) I3=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_58_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(67) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(66) D=cmd_serial_host0.resp_buff_ff_CQZ_59_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(66) I2=cmd_serial_host0.resp_buff_ff_CQZ_59_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_59_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_59_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(120) O=cmd_serial_host0.resp_buff_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=cmd_serial_host0.counter(31) I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000001000100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(119) D=cmd_serial_host0.resp_buff_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(65) D=cmd_serial_host0.resp_buff_ff_CQZ_60_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(65) I2=cmd_serial_host0.resp_buff_ff_CQZ_60_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_60_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_60_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(64) D=cmd_serial_host0.resp_buff_ff_CQZ_61_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(64) I3=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_61_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(63) D=cmd_serial_host0.resp_buff_ff_CQZ_62_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(63) I3=cmd_serial_host0.resp_buff_ff_CQZ_62_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_62_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(63) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_62_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(62) D=cmd_serial_host0.resp_buff_ff_CQZ_63_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(62) I2=cmd_serial_host0.resp_buff_ff_CQZ_63_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_63_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_63_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(61) D=cmd_serial_host0.resp_buff_ff_CQZ_64_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(61) I3=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_64_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(60) D=cmd_serial_host0.resp_buff_ff_CQZ_65_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(60) I2=cmd_serial_host0.resp_buff_ff_CQZ_65_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_65_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_65_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(59) D=cmd_serial_host0.resp_buff_ff_CQZ_66_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(59) I3=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_66_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(59) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(58) D=cmd_serial_host0.resp_buff_ff_CQZ_67_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(58) I2=cmd_serial_host0.resp_buff_ff_CQZ_67_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_67_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_67_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(57) D=cmd_serial_host0.resp_buff_ff_CQZ_68_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(57) I2=cmd_serial_host0.resp_buff_ff_CQZ_68_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_68_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_68_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(56) D=cmd_serial_host0.resp_buff_ff_CQZ_69_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(56) I3=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_69_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_6_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(119) I3=cmd_serial_host0.cmd_dat_reg O=cmd_serial_host0.resp_buff_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(118) D=cmd_serial_host0.resp_buff_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(55) D=cmd_serial_host0.resp_buff_ff_CQZ_70_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(55) I3=cmd_serial_host0.resp_buff_ff_CQZ_70_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_70_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(55) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_70_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(54) D=cmd_serial_host0.resp_buff_ff_CQZ_71_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(54) I2=cmd_serial_host0.resp_buff_ff_CQZ_71_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_71_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_71_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(53) D=cmd_serial_host0.resp_buff_ff_CQZ_72_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(53) I3=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_72_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(52) D=cmd_serial_host0.resp_buff_ff_CQZ_73_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(52) I2=cmd_serial_host0.resp_buff_ff_CQZ_73_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_73_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_73_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(51) D=cmd_serial_host0.resp_buff_ff_CQZ_74_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(51) I3=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_74_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(51) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(50) D=cmd_serial_host0.resp_buff_ff_CQZ_75_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(50) I2=cmd_serial_host0.resp_buff_ff_CQZ_75_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_75_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_75_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(49) D=cmd_serial_host0.resp_buff_ff_CQZ_76_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(49) I2=cmd_serial_host0.resp_buff_ff_CQZ_76_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_76_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_76_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(48) D=cmd_serial_host0.resp_buff_ff_CQZ_77_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(48) I3=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_77_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(47) D=cmd_serial_host0.resp_buff_ff_CQZ_78_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(47) I3=cmd_serial_host0.resp_buff_ff_CQZ_78_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_78_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(47) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_78_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(46) D=cmd_serial_host0.resp_buff_ff_CQZ_79_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(46) I2=cmd_serial_host0.resp_buff_ff_CQZ_79_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_79_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_79_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(118) I2=cmd_serial_host0.resp_buff_ff_CQZ_7_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_7_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(117) D=cmd_serial_host0.resp_buff_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(45) D=cmd_serial_host0.resp_buff_ff_CQZ_80_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(45) I3=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_80_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(44) D=cmd_serial_host0.resp_buff_ff_CQZ_81_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(44) I2=cmd_serial_host0.resp_buff_ff_CQZ_81_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_81_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_81_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(43) D=cmd_serial_host0.resp_buff_ff_CQZ_82_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(43) I3=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_82_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(43) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(42) D=cmd_serial_host0.resp_buff_ff_CQZ_83_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(42) I2=cmd_serial_host0.resp_buff_ff_CQZ_83_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_83_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_83_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(41) D=cmd_serial_host0.resp_buff_ff_CQZ_84_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(41) I2=cmd_serial_host0.resp_buff_ff_CQZ_84_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_84_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_84_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(40) D=cmd_serial_host0.resp_buff_ff_CQZ_85_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(40) I3=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_85_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(39) D=cmd_serial_host0.resp_buff_ff_CQZ_86_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(39) I3=cmd_serial_host0.resp_buff_ff_CQZ_86_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_86_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(39) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_86_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(38) D=cmd_serial_host0.resp_buff_ff_CQZ_87_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(38) I2=cmd_serial_host0.resp_buff_ff_CQZ_87_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_87_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_87_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(37) D=cmd_serial_host0.resp_buff_ff_CQZ_88_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(37) I3=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_88_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(36) D=cmd_serial_host0.resp_buff_ff_CQZ_89_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(36) I2=cmd_serial_host0.resp_buff_ff_CQZ_89_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_89_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_89_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(117) I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(3) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100101100000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(116) D=cmd_serial_host0.resp_buff_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(35) D=cmd_serial_host0.resp_buff_ff_CQZ_90_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(35) I3=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_90_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(35) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(34) D=cmd_serial_host0.resp_buff_ff_CQZ_91_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(34) I2=cmd_serial_host0.resp_buff_ff_CQZ_91_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_91_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_91_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(33) D=cmd_serial_host0.resp_buff_ff_CQZ_92_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(33) I2=cmd_serial_host0.resp_buff_ff_CQZ_92_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_92_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_92_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(32) D=cmd_serial_host0.resp_buff_ff_CQZ_93_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(32) I3=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_93_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(31) D=cmd_serial_host0.resp_buff_ff_CQZ_94_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(31) I3=cmd_serial_host0.resp_buff_ff_CQZ_94_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_94_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(31) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_94_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(30) D=cmd_serial_host0.resp_buff_ff_CQZ_95_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(30) I2=cmd_serial_host0.resp_buff_ff_CQZ_95_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_95_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_95_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(29) D=cmd_serial_host0.resp_buff_ff_CQZ_96_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(29) I3=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_96_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(28) D=cmd_serial_host0.resp_buff_ff_CQZ_97_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(28) I2=cmd_serial_host0.resp_buff_ff_CQZ_97_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_97_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_97_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(27) D=cmd_serial_host0.resp_buff_ff_CQZ_98_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(27) I3=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_98_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(1) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(27) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000100011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_buff(26) D=cmd_serial_host0.resp_buff_ff_CQZ_99_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(26) I2=cmd_serial_host0.resp_buff_ff_CQZ_99_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_99_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_99_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(116) I2=cmd_serial_host0.resp_buff_ff_CQZ_9_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_9_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(125) O=cmd_serial_host0.resp_buff_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(31) D=cmd_serial_host0.resp_idx_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(30) D=cmd_serial_host0.resp_idx_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(21) D=cmd_serial_host0.resp_idx_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(21) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(20) D=cmd_serial_host0.resp_idx_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(20) I3=cmd_serial_host0.resp_idx_ff_CQZ_11_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_idx(17) I2=cmd_serial_host0.resp_idx(18) I3=cmd_serial_host0.resp_idx(19) O=cmd_serial_host0.resp_idx_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(19) D=cmd_serial_host0.resp_idx_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.resp_idx_ff_CQZ_12_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_idx(17) I2=cmd_serial_host0.resp_idx(18) I3=cmd_serial_host0.resp_idx(19) O=cmd_serial_host0.resp_idx_ff_CQZ_12_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(18) D=cmd_serial_host0.resp_idx_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_idx(17) I2=cmd_serial_host0.resp_idx(18) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(17) D=cmd_serial_host0.resp_idx_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(17) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_idx_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(16) D=cmd_serial_host0.resp_idx_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(15) I2=cmd_serial_host0.resp_idx(16) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(15) D=cmd_serial_host0.resp_idx_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(15) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(16) I2=cmd_serial_host0.resp_idx(15) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx(17) I1=cmd_serial_host0.resp_idx(18) I2=cmd_serial_host0.resp_idx(19) I3=cmd_serial_host0.resp_idx(20) O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(10) I2=cmd_serial_host0.resp_idx(9) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(15) I3=cmd_serial_host0.resp_idx(16) O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx(11) I1=cmd_serial_host0.resp_idx(12) I2=cmd_serial_host0.resp_idx(13) I3=cmd_serial_host0.resp_idx(14) O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(14) D=cmd_serial_host0.resp_idx_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_18_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(13) I2=cmd_serial_host0.resp_idx(14) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(13) D=cmd_serial_host0.resp_idx_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(13) I3=cmd_serial_host0.resp_idx_ff_CQZ_18_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(12) I2=cmd_serial_host0.resp_idx(11) I3=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_18_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(12) D=cmd_serial_host0.resp_idx_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(11) I2=cmd_serial_host0.resp_idx(12) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.resp_idx(29) I2=cmd_serial_host0.resp_idx(30) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(29) D=cmd_serial_host0.resp_idx_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(11) D=cmd_serial_host0.resp_idx_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(11) I3=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(10) D=cmd_serial_host0.resp_idx_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(9) I2=cmd_serial_host0.resp_idx(10) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(9) D=cmd_serial_host0.resp_idx_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(9) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(8) D=cmd_serial_host0.resp_idx_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(7) I2=cmd_serial_host0.resp_idx(8) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(7) D=cmd_serial_host0.resp_idx_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(8) I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(10) I2=cmd_serial_host0.resp_idx(9) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(6) D=cmd_serial_host0.resp_idx_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_25_D_LUT4_O_I0 I1=cmd_serial_host0.resp_idx(5) I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(6) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_idx_ff_CQZ_25_D_LUT4_O_I0 O=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_25_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(5) D=cmd_serial_host0.resp_idx_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(4) D=cmd_serial_host0.resp_idx_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(3) D=cmd_serial_host0.resp_idx_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(2) D=cmd_serial_host0.resp_idx_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(1) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(29) I3=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0 O=cmd_serial_host0.resp_idx_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(28) D=cmd_serial_host0.resp_idx_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(1) D=cmd_serial_host0.resp_idx_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(1) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_idx_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(0) D=cmd_serial_host0.resp_idx_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_idx_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(28) I3=cmd_serial_host0.resp_idx_ff_CQZ_3_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(28) I3=cmd_serial_host0.resp_idx_ff_CQZ_3_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx_ff_CQZ_4_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(27) D=cmd_serial_host0.resp_idx_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx_ff_CQZ_4_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(26) I3=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(26) D=cmd_serial_host0.resp_idx_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(26) I3=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(26) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(15) O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(7) I2=cmd_serial_host0.resp_idx(8) I3=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0 O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(8) I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(22) I2=cmd_serial_host0.resp_idx(21) I3=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(25) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.resp_idx(23) O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(25) D=cmd_serial_host0.resp_idx_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.resp_idx_ff_CQZ_6_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(23) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.resp_idx(25) O=cmd_serial_host0.resp_idx_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(24) D=cmd_serial_host0.resp_idx_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(23) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(23) D=cmd_serial_host0.resp_idx_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(23) I3=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(22) I2=cmd_serial_host0.resp_idx(21) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_idx(22) D=cmd_serial_host0.resp_idx_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(21) I2=cmd_serial_host0.resp_idx(22) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(31) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1 I1=cmd_serial_host0.resp_idx(31) I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx(28) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O I1=cmd_serial_host0.resp_idx(21) I2=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_I2 I3=cmd_serial_host0.resp_idx(26) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011101110110000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx(22) I1=cmd_serial_host0.resp_idx(23) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.resp_idx(25) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(10) I3=cmd_serial_host0.resp_idx(9) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=cmd_serial_host0.resp_idx(11) I1=cmd_serial_host0.resp_idx(12) I2=cmd_serial_host0.resp_idx(13) I3=cmd_serial_host0.resp_idx(14) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(8) I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(30) I3=cmd_serial_host0.resp_idx(29) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(31) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(30) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(21) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(20) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(19) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(18) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(17) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(16) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(15) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(14) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(13) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(12) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(29) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(11) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(10) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(9) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(8) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(7) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(6) D=sd_cmd_master0.long_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(5) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(4) D=sd_cmd_master0.long_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(3) D=sd_cmd_master0.long_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(28) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(27) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(26) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(25) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(24) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(23) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_serial_host0.resp_len(22) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(119) D=cmd_serial_host0.response_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(118) D=cmd_serial_host0.response_o_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(109) D=cmd_serial_host0.response_o_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(19) D=cmd_serial_host0.response_o_ff_CQZ_100_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(19) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_100_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(18) D=cmd_serial_host0.response_o_ff_CQZ_101_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(18) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_101_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(17) D=cmd_serial_host0.response_o_ff_CQZ_102_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(17) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_102_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(16) D=cmd_serial_host0.response_o_ff_CQZ_103_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(16) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_103_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(15) D=cmd_serial_host0.response_o_ff_CQZ_104_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(15) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_104_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(14) D=cmd_serial_host0.response_o_ff_CQZ_105_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(14) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_105_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(13) D=cmd_serial_host0.response_o_ff_CQZ_106_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(13) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_106_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(12) D=cmd_serial_host0.response_o_ff_CQZ_107_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(12) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_107_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(11) D=cmd_serial_host0.response_o_ff_CQZ_108_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(11) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_108_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(10) D=cmd_serial_host0.response_o_ff_CQZ_109_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(10) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_109_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(109) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(108) D=cmd_serial_host0.response_o_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(9) D=cmd_serial_host0.response_o_ff_CQZ_110_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(9) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_110_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(8) D=cmd_serial_host0.response_o_ff_CQZ_111_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(8) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_111_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(7) D=cmd_serial_host0.response_o_ff_CQZ_112_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(7) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_112_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(6) D=cmd_serial_host0.response_o_ff_CQZ_113_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(6) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_113_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(5) D=cmd_serial_host0.response_o_ff_CQZ_114_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(5) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_114_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(4) D=cmd_serial_host0.response_o_ff_CQZ_115_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(4) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_115_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(3) D=cmd_serial_host0.response_o_ff_CQZ_116_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(3) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_116_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(2) D=cmd_serial_host0.response_o_ff_CQZ_117_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(2) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_117_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(1) D=cmd_serial_host0.response_o_ff_CQZ_118_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(1) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_118_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(0) D=cmd_serial_host0.response_o_ff_CQZ_119_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(0) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_119_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(108) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(107) D=cmd_serial_host0.response_o_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(107) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(106) D=cmd_serial_host0.response_o_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(106) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(105) D=cmd_serial_host0.response_o_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(105) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(104) D=cmd_serial_host0.response_o_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(104) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(103) D=cmd_serial_host0.response_o_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(103) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(102) D=cmd_serial_host0.response_o_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(102) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(101) D=cmd_serial_host0.response_o_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(101) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(100) D=cmd_serial_host0.response_o_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(100) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(118) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(117) D=cmd_serial_host0.response_o_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(99) D=cmd_serial_host0.response_o_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(99) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(98) D=cmd_serial_host0.response_o_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(98) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(97) D=cmd_serial_host0.response_o_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(97) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(96) D=cmd_serial_host0.response_o_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(96) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(95) D=cmd_serial_host0.response_o_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(95) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(94) D=cmd_serial_host0.response_o_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(94) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(93) D=cmd_serial_host0.response_o_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(93) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(92) D=cmd_serial_host0.response_o_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(92) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(91) D=cmd_serial_host0.response_o_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(91) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(90) D=cmd_serial_host0.response_o_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(90) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(117) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(116) D=cmd_serial_host0.response_o_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(89) D=cmd_serial_host0.response_o_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(89) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(88) D=cmd_serial_host0.response_o_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(88) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(87) D=cmd_serial_host0.response_o_ff_CQZ_32_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(87) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_32_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(86) D=cmd_serial_host0.response_o_ff_CQZ_33_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(86) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_33_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(85) D=cmd_serial_host0.response_o_ff_CQZ_34_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(85) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_34_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(84) D=cmd_serial_host0.response_o_ff_CQZ_35_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(84) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_35_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(83) D=cmd_serial_host0.response_o_ff_CQZ_36_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(83) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_36_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(82) D=cmd_serial_host0.response_o_ff_CQZ_37_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(82) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_37_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(81) D=cmd_serial_host0.response_o_ff_CQZ_38_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(81) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_38_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(80) D=cmd_serial_host0.response_o_ff_CQZ_39_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(80) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_39_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(116) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(115) D=cmd_serial_host0.response_o_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(79) D=cmd_serial_host0.response_o_ff_CQZ_40_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(79) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_40_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(78) D=cmd_serial_host0.response_o_ff_CQZ_41_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(78) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_41_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(77) D=cmd_serial_host0.response_o_ff_CQZ_42_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(77) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_42_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(76) D=cmd_serial_host0.response_o_ff_CQZ_43_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(76) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_43_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(75) D=cmd_serial_host0.response_o_ff_CQZ_44_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(75) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_44_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(74) D=cmd_serial_host0.response_o_ff_CQZ_45_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(74) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_45_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(73) D=cmd_serial_host0.response_o_ff_CQZ_46_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(73) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_46_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(72) D=cmd_serial_host0.response_o_ff_CQZ_47_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(72) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_47_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(71) D=cmd_serial_host0.response_o_ff_CQZ_48_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(71) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_48_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(70) D=cmd_serial_host0.response_o_ff_CQZ_49_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(70) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_49_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(115) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(114) D=cmd_serial_host0.response_o_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(69) D=cmd_serial_host0.response_o_ff_CQZ_50_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(69) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_50_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(68) D=cmd_serial_host0.response_o_ff_CQZ_51_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(68) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_51_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(67) D=cmd_serial_host0.response_o_ff_CQZ_52_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(67) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_52_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(66) D=cmd_serial_host0.response_o_ff_CQZ_53_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(66) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_53_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(65) D=cmd_serial_host0.response_o_ff_CQZ_54_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(65) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_54_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(64) D=cmd_serial_host0.response_o_ff_CQZ_55_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(64) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_55_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(63) D=cmd_serial_host0.response_o_ff_CQZ_56_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(63) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_56_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(62) D=cmd_serial_host0.response_o_ff_CQZ_57_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(62) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_57_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(61) D=cmd_serial_host0.response_o_ff_CQZ_58_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(61) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_58_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(60) D=cmd_serial_host0.response_o_ff_CQZ_59_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(60) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_59_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(114) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(113) D=cmd_serial_host0.response_o_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(59) D=cmd_serial_host0.response_o_ff_CQZ_60_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(59) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_60_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(58) D=cmd_serial_host0.response_o_ff_CQZ_61_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(58) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_61_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(57) D=cmd_serial_host0.response_o_ff_CQZ_62_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(57) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_62_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(56) D=cmd_serial_host0.response_o_ff_CQZ_63_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(56) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_63_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(55) D=cmd_serial_host0.response_o_ff_CQZ_64_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(55) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_64_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(54) D=cmd_serial_host0.response_o_ff_CQZ_65_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(54) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_65_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(53) D=cmd_serial_host0.response_o_ff_CQZ_66_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(53) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_66_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(52) D=cmd_serial_host0.response_o_ff_CQZ_67_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(52) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_67_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(51) D=cmd_serial_host0.response_o_ff_CQZ_68_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(51) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_68_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(50) D=cmd_serial_host0.response_o_ff_CQZ_69_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(50) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_69_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(113) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(112) D=cmd_serial_host0.response_o_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(49) D=cmd_serial_host0.response_o_ff_CQZ_70_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(49) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_70_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(48) D=cmd_serial_host0.response_o_ff_CQZ_71_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(48) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_71_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(47) D=cmd_serial_host0.response_o_ff_CQZ_72_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(47) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_72_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(46) D=cmd_serial_host0.response_o_ff_CQZ_73_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(46) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_73_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(45) D=cmd_serial_host0.response_o_ff_CQZ_74_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(45) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_74_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(44) D=cmd_serial_host0.response_o_ff_CQZ_75_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(44) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_75_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(43) D=cmd_serial_host0.response_o_ff_CQZ_76_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(43) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_76_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(42) D=cmd_serial_host0.response_o_ff_CQZ_77_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(42) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_77_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(41) D=cmd_serial_host0.response_o_ff_CQZ_78_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(41) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_78_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(40) D=cmd_serial_host0.response_o_ff_CQZ_79_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(40) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_79_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(112) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(111) D=cmd_serial_host0.response_o_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(39) D=cmd_serial_host0.response_o_ff_CQZ_80_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(39) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_80_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(38) D=cmd_serial_host0.response_o_ff_CQZ_81_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(38) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_81_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(37) D=cmd_serial_host0.response_o_ff_CQZ_82_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(37) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_82_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(36) D=cmd_serial_host0.response_o_ff_CQZ_83_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(36) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_83_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(35) D=cmd_serial_host0.response_o_ff_CQZ_84_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(35) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_84_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(34) D=cmd_serial_host0.response_o_ff_CQZ_85_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(34) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_85_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(33) D=cmd_serial_host0.response_o_ff_CQZ_86_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(33) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_86_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(32) D=cmd_serial_host0.response_o_ff_CQZ_87_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(32) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_87_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(31) D=cmd_serial_host0.response_o_ff_CQZ_88_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(31) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_88_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(30) D=cmd_serial_host0.response_o_ff_CQZ_89_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(30) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_89_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(111) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(110) D=cmd_serial_host0.response_o_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_response(29) D=cmd_serial_host0.response_o_ff_CQZ_90_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(29) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_90_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(28) D=cmd_serial_host0.response_o_ff_CQZ_91_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(28) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_91_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(27) D=cmd_serial_host0.response_o_ff_CQZ_92_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(27) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_92_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(26) D=cmd_serial_host0.response_o_ff_CQZ_93_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(26) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_93_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(25) D=cmd_serial_host0.response_o_ff_CQZ_94_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(25) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_94_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(24) D=cmd_serial_host0.response_o_ff_CQZ_95_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(24) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_95_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(23) D=cmd_serial_host0.response_o_ff_CQZ_96_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(23) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_96_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(22) D=cmd_serial_host0.response_o_ff_CQZ_97_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(22) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_97_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(21) D=cmd_serial_host0.response_o_ff_CQZ_98_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(21) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_98_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_response(20) D=cmd_serial_host0.response_o_ff_CQZ_99_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(20) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_99_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(110) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(119) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.go_idle_o I3=sd_cmd_master0.rst O=cmd_serial_host0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=cmd_serial_host0.state(6) D=cmd_serial_host0.next_state(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.state(5) D=cmd_serial_host0.next_state(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.state(4) D=cmd_serial_host0.next_state(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.state(3) D=cmd_serial_host0.next_state(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.state(2) D=cmd_serial_host0.next_state(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.state(1) D=cmd_serial_host0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_serial_host0.state(0) D=cmd_serial_host0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.with_response I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.next_state_LUT4_O_3_I2 O=cmd_serial_host0.next_state_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111101110111
|
|
.subckt ff CQZ=cmd_serial_host0.with_response D=sd_cmd_master0.expect_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_start_cross.sync_clk_b(2) D=cmd_start_cross.sync_clk_b(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_start_cross.sync_clk_b(1) D=cmd_start_cross.sync_clk_b(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_start_cross.sync_clk_b(0) D=cmd_start_cross.toggle_clk_a QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_start_cross.toggle_clk_a I2=cmd_start_edge.sig_reg(0) I3=cmd_start_edge.sig_reg(1) O=cmd_start_cross.toggle_clk_a_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt ff CQZ=cmd_start_cross.toggle_clk_a D=cmd_start_cross.toggle_clk_a_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:57.1-63.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_start_edge.sig_reg(1) D=cmd_start_edge.sig_reg(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:379.13-379.110|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=cmd_start_edge.sig_reg(0) D=cmd_start_edge.sig QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:379.13-379.110|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](13) D=command_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](12) D=command_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](2) D=command_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](1) D=command_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](0) D=command_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](11) D=command_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](10) D=command_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](9) D=command_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](8) D=command_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](6) D=command_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](5) D=command_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](4) D=command_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.sync_clk_b[0](3) D=command_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(13) D=command_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(12) D=command_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(2) D=command_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(1) D=command_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(0) D=command_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(11) D=command_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(10) D=command_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(9) D=command_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(8) D=command_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(6) D=command_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(5) D=command_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(4) D=command_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.out(3) D=command_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=controll_setting_reg_cross.sync_clk_b[0](0) D=controll_setting_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:394.29-394.143|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=data_int_rst_cross.sync_clk_b(1) I3=data_int_rst_cross.sync_clk_b(2) O=sd_data_master0.trans_done_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt ff CQZ=data_int_rst_cross.sync_clk_b(2) D=data_int_rst_cross.sync_clk_b(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_rst_cross.sync_clk_b(1) D=data_int_rst_cross.sync_clk_b(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_rst_cross.sync_clk_b(0) D=data_int_rst_cross.toggle_clk_a QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=data_int_rst_cross.toggle_clk_a I2=data_int_rst_edge.sig_reg(0) I3=data_int_rst_edge.sig_reg(1) O=data_int_rst_cross.toggle_clk_a_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt ff CQZ=data_int_rst_cross.toggle_clk_a D=data_int_rst_cross.toggle_clk_a_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:57.1-63.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_rst_edge.sig_reg(1) D=data_int_rst_edge.sig_reg(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:380.13-380.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_rst_edge.sig_reg(0) D=data_int_rst_edge.sig QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:380.13-380.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_status_reg_cross.sync_clk_b[0](2) D=data_int_status_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_status_reg_cross.sync_clk_b[0](1) D=data_int_status_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_status_reg_cross.sync_clk_b[0](0) D=data_int_status_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_status_reg_cross.out(2) D=data_int_status_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_status_reg_cross.out(1) D=data_int_status_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=data_int_status_reg_cross.out(0) D=data_int_status_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](31) D=dma_addr_reg_cross.in(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](30) D=dma_addr_reg_cross.in(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](21) D=dma_addr_reg_cross.in(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](20) D=dma_addr_reg_cross.in(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](19) D=dma_addr_reg_cross.in(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](18) D=dma_addr_reg_cross.in(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](17) D=dma_addr_reg_cross.in(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](16) D=dma_addr_reg_cross.in(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](15) D=dma_addr_reg_cross.in(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](14) D=dma_addr_reg_cross.in(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](13) D=dma_addr_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](12) D=dma_addr_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](29) D=dma_addr_reg_cross.in(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](11) D=dma_addr_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](10) D=dma_addr_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](9) D=dma_addr_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](8) D=dma_addr_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](7) D=dma_addr_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](6) D=dma_addr_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](5) D=dma_addr_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](4) D=dma_addr_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](3) D=dma_addr_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](2) D=dma_addr_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](28) D=dma_addr_reg_cross.in(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](1) D=dma_addr_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](0) D=dma_addr_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](27) D=dma_addr_reg_cross.in(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](26) D=dma_addr_reg_cross.in(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](25) D=dma_addr_reg_cross.in(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](24) D=dma_addr_reg_cross.in(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](23) D=dma_addr_reg_cross.in(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](22) D=dma_addr_reg_cross.in(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(31) D=dma_addr_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(30) D=dma_addr_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(21) D=dma_addr_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(20) D=dma_addr_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(19) D=dma_addr_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(18) D=dma_addr_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(17) D=dma_addr_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(16) D=dma_addr_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(15) D=dma_addr_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(14) D=dma_addr_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(13) D=dma_addr_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(12) D=dma_addr_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(29) D=dma_addr_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(11) D=dma_addr_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(10) D=dma_addr_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(9) D=dma_addr_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(8) D=dma_addr_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(7) D=dma_addr_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(6) D=dma_addr_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(5) D=dma_addr_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(4) D=dma_addr_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(3) D=dma_addr_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(2) D=dma_addr_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(28) D=dma_addr_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(1) D=dma_addr_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(0) D=dma_addr_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(27) D=dma_addr_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(26) D=dma_addr_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(25) D=dma_addr_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(24) D=dma_addr_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(23) D=dma_addr_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=dma_addr_reg_cross.out(22) D=dma_addr_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=cmd_int_status_reg_cross.out(0) I1=cmd_int_enable_reg_cross.in(0) I2=int_cmd_LUT4_O_I2 I3=int_cmd_LUT4_O_I3 O=$iopadmap$int_cmd
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111111111111
|
|
.subckt LUT4 I0=cmd_int_status_reg_cross.out(1) I1=cmd_int_enable_reg_cross.in(1) I2=cmd_int_status_reg_cross.out(4) I3=cmd_int_enable_reg_cross.in(4) O=int_cmd_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=cmd_int_status_reg_cross.out(2) I1=cmd_int_enable_reg_cross.in(2) I2=cmd_int_status_reg_cross.out(3) I3=cmd_int_enable_reg_cross.in(3) O=int_cmd_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=int_data_LUT4_O_I1 I2=data_int_status_reg_cross.out(2) I3=data_int_enable_reg_cross.in(2) O=$iopadmap$int_data
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10001111
|
|
.subckt LUT4 I0=data_int_status_reg_cross.out(0) I1=data_int_enable_reg_cross.in(0) I2=data_int_status_reg_cross.out(1) I3=data_int_enable_reg_cross.in(1) O=int_data_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset(0) I3=dma_addr_reg_cross.out(0) O=sd_fifo_filler0.wbm_adr_o(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_2_I3 I1=sd_fifo_filler0.offset(30) I2=dma_addr_reg_cross.out(30) I3=m_wb_adr_o_LUT4_O_1_I3 O=sd_fifo_filler0.wbm_adr_o(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011111101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_10_I0 I1=m_wb_adr_o_LUT4_O_10_I1 I2=sd_fifo_filler0.offset(22) I3=dma_addr_reg_cross.out(22) O=sd_fifo_filler0.wbm_adr_o(22)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111011100001
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_12_I3 I1=sd_fifo_filler0.offset(20) I2=dma_addr_reg_cross.out(20) I3=m_wb_adr_o_LUT4_O_10_I0_LUT4_O_I3 O=m_wb_adr_o_LUT4_O_10_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(21) I3=sd_fifo_filler0.offset(21) O=m_wb_adr_o_LUT4_O_10_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(21) I3=sd_fifo_filler0.offset(21) O=m_wb_adr_o_LUT4_O_10_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(21) I2=sd_fifo_filler0.offset(21) I3=m_wb_adr_o_LUT4_O_11_I3 O=sd_fifo_filler0.wbm_adr_o(21)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(20) I2=sd_fifo_filler0.offset(20) I3=m_wb_adr_o_LUT4_O_12_I3 O=m_wb_adr_o_LUT4_O_11_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(20) I2=sd_fifo_filler0.offset(20) I3=m_wb_adr_o_LUT4_O_12_I3 O=sd_fifo_filler0.wbm_adr_o(20)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(19) I1=dma_addr_reg_cross.out(19) I2=m_wb_adr_o_LUT4_O_13_I0 I3=m_wb_adr_o_LUT4_O_13_I1 O=m_wb_adr_o_LUT4_O_12_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_13_I0 I1=m_wb_adr_o_LUT4_O_13_I1 I2=sd_fifo_filler0.offset(19) I3=dma_addr_reg_cross.out(19) O=sd_fifo_filler0.wbm_adr_o(19)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_15_I3 I1=sd_fifo_filler0.offset(17) I2=dma_addr_reg_cross.out(17) I3=m_wb_adr_o_LUT4_O_14_I3 O=m_wb_adr_o_LUT4_O_13_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(18) I3=sd_fifo_filler0.offset(18) O=m_wb_adr_o_LUT4_O_13_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_15_I3 I1=sd_fifo_filler0.offset(17) I2=dma_addr_reg_cross.out(17) I3=m_wb_adr_o_LUT4_O_14_I3 O=sd_fifo_filler0.wbm_adr_o(18)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100000010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(18) I3=sd_fifo_filler0.offset(18) O=m_wb_adr_o_LUT4_O_14_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(17) I2=sd_fifo_filler0.offset(17) I3=m_wb_adr_o_LUT4_O_15_I3 O=sd_fifo_filler0.wbm_adr_o(17)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(16) I1=dma_addr_reg_cross.out(16) I2=m_wb_adr_o_LUT4_O_16_I0 I3=m_wb_adr_o_LUT4_O_16_I1 O=m_wb_adr_o_LUT4_O_15_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_16_I0 I1=m_wb_adr_o_LUT4_O_16_I1 I2=sd_fifo_filler0.offset(16) I3=dma_addr_reg_cross.out(16) O=sd_fifo_filler0.wbm_adr_o(16)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_18_I3 I1=sd_fifo_filler0.offset(14) I2=dma_addr_reg_cross.out(14) I3=m_wb_adr_o_LUT4_O_16_I0_LUT4_O_I3 O=m_wb_adr_o_LUT4_O_16_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(15) I3=sd_fifo_filler0.offset(15) O=m_wb_adr_o_LUT4_O_16_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(15) I3=sd_fifo_filler0.offset(15) O=m_wb_adr_o_LUT4_O_16_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(15) I2=sd_fifo_filler0.offset(15) I3=m_wb_adr_o_LUT4_O_17_I3 O=sd_fifo_filler0.wbm_adr_o(15)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(14) I2=sd_fifo_filler0.offset(14) I3=m_wb_adr_o_LUT4_O_18_I3 O=m_wb_adr_o_LUT4_O_17_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(14) I2=sd_fifo_filler0.offset(14) I3=m_wb_adr_o_LUT4_O_18_I3 O=sd_fifo_filler0.wbm_adr_o(14)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(13) I1=dma_addr_reg_cross.out(13) I2=m_wb_adr_o_LUT4_O_19_I0 I3=m_wb_adr_o_LUT4_O_19_I1 O=m_wb_adr_o_LUT4_O_18_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_19_I0 I1=m_wb_adr_o_LUT4_O_19_I1 I2=sd_fifo_filler0.offset(13) I3=dma_addr_reg_cross.out(13) O=sd_fifo_filler0.wbm_adr_o(13)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_21_I3 I1=sd_fifo_filler0.offset(11) I2=dma_addr_reg_cross.out(11) I3=m_wb_adr_o_LUT4_O_20_I3 O=m_wb_adr_o_LUT4_O_19_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(12) I3=sd_fifo_filler0.offset(12) O=m_wb_adr_o_LUT4_O_19_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(31) I3=sd_fifo_filler0.offset(31) O=m_wb_adr_o_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(30) I2=sd_fifo_filler0.offset(30) I3=m_wb_adr_o_LUT4_O_2_I3 O=sd_fifo_filler0.wbm_adr_o(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_21_I3 I1=sd_fifo_filler0.offset(11) I2=dma_addr_reg_cross.out(11) I3=m_wb_adr_o_LUT4_O_20_I3 O=sd_fifo_filler0.wbm_adr_o(12)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100000010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(12) I3=sd_fifo_filler0.offset(12) O=m_wb_adr_o_LUT4_O_20_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(11) I2=sd_fifo_filler0.offset(11) I3=m_wb_adr_o_LUT4_O_21_I3 O=sd_fifo_filler0.wbm_adr_o(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(10) I1=dma_addr_reg_cross.out(10) I2=m_wb_adr_o_LUT4_O_22_I0 I3=m_wb_adr_o_LUT4_O_22_I1 O=m_wb_adr_o_LUT4_O_21_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_22_I0 I1=m_wb_adr_o_LUT4_O_22_I1 I2=sd_fifo_filler0.offset(10) I3=dma_addr_reg_cross.out(10) O=sd_fifo_filler0.wbm_adr_o(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_24_I3 I1=sd_fifo_filler0.offset(8) I2=dma_addr_reg_cross.out(8) I3=m_wb_adr_o_LUT4_O_22_I0_LUT4_O_I3 O=m_wb_adr_o_LUT4_O_22_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(9) I3=sd_fifo_filler0.offset(9) O=m_wb_adr_o_LUT4_O_22_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(9) I3=sd_fifo_filler0.offset(9) O=m_wb_adr_o_LUT4_O_22_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(9) I2=sd_fifo_filler0.offset(9) I3=m_wb_adr_o_LUT4_O_23_I3 O=sd_fifo_filler0.wbm_adr_o(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(8) I2=sd_fifo_filler0.offset(8) I3=m_wb_adr_o_LUT4_O_24_I3 O=m_wb_adr_o_LUT4_O_23_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(8) I2=sd_fifo_filler0.offset(8) I3=m_wb_adr_o_LUT4_O_24_I3 O=sd_fifo_filler0.wbm_adr_o(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(7) I1=dma_addr_reg_cross.out(7) I2=m_wb_adr_o_LUT4_O_25_I0 I3=m_wb_adr_o_LUT4_O_25_I1 O=m_wb_adr_o_LUT4_O_24_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_25_I0 I1=m_wb_adr_o_LUT4_O_25_I1 I2=sd_fifo_filler0.offset(7) I3=dma_addr_reg_cross.out(7) O=sd_fifo_filler0.wbm_adr_o(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_27_I3 I1=sd_fifo_filler0.offset(5) I2=dma_addr_reg_cross.out(5) I3=m_wb_adr_o_LUT4_O_26_I3 O=m_wb_adr_o_LUT4_O_25_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(6) I3=sd_fifo_filler0.offset(6) O=m_wb_adr_o_LUT4_O_25_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_27_I3 I1=sd_fifo_filler0.offset(5) I2=dma_addr_reg_cross.out(5) I3=m_wb_adr_o_LUT4_O_26_I3 O=sd_fifo_filler0.wbm_adr_o(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100000010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(6) I3=sd_fifo_filler0.offset(6) O=m_wb_adr_o_LUT4_O_26_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(5) I2=sd_fifo_filler0.offset(5) I3=m_wb_adr_o_LUT4_O_27_I3 O=sd_fifo_filler0.wbm_adr_o(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(4) I1=dma_addr_reg_cross.out(4) I2=m_wb_adr_o_LUT4_O_28_I0 I3=m_wb_adr_o_LUT4_O_28_I1 O=m_wb_adr_o_LUT4_O_27_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_28_I0 I1=m_wb_adr_o_LUT4_O_28_I1 I2=sd_fifo_filler0.offset(4) I3=dma_addr_reg_cross.out(4) O=sd_fifo_filler0.wbm_adr_o(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_30_I3 I1=sd_fifo_filler0.offset(2) I2=dma_addr_reg_cross.out(2) I3=m_wb_adr_o_LUT4_O_29_I3 O=m_wb_adr_o_LUT4_O_28_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(3) I3=sd_fifo_filler0.offset(3) O=m_wb_adr_o_LUT4_O_28_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_30_I3 I1=sd_fifo_filler0.offset(2) I2=dma_addr_reg_cross.out(2) I3=m_wb_adr_o_LUT4_O_29_I3 O=sd_fifo_filler0.wbm_adr_o(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010000101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(3) I3=sd_fifo_filler0.offset(3) O=m_wb_adr_o_LUT4_O_29_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(29) I1=dma_addr_reg_cross.out(29) I2=m_wb_adr_o_LUT4_O_3_I0 I3=m_wb_adr_o_LUT4_O_3_I1 O=m_wb_adr_o_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_3_I0 I1=m_wb_adr_o_LUT4_O_3_I1 I2=sd_fifo_filler0.offset(29) I3=dma_addr_reg_cross.out(29) O=sd_fifo_filler0.wbm_adr_o(29)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(2) I2=sd_fifo_filler0.offset(2) I3=m_wb_adr_o_LUT4_O_30_I3 O=sd_fifo_filler0.wbm_adr_o(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=dma_addr_reg_cross.out(1) I1=sd_fifo_filler0.offset(1) I2=dma_addr_reg_cross.out(0) I3=sd_fifo_filler0.offset(0) O=m_wb_adr_o_LUT4_O_30_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=dma_addr_reg_cross.out(0) I1=sd_fifo_filler0.offset(0) I2=dma_addr_reg_cross.out(1) I3=sd_fifo_filler0.offset(1) O=sd_fifo_filler0.wbm_adr_o(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011101111000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_5_I3 I1=sd_fifo_filler0.offset(27) I2=dma_addr_reg_cross.out(27) I3=m_wb_adr_o_LUT4_O_4_I3 O=m_wb_adr_o_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(28) I3=sd_fifo_filler0.offset(28) O=m_wb_adr_o_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_5_I3 I1=sd_fifo_filler0.offset(27) I2=dma_addr_reg_cross.out(27) I3=m_wb_adr_o_LUT4_O_4_I3 O=sd_fifo_filler0.wbm_adr_o(28)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100000010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(28) I3=sd_fifo_filler0.offset(28) O=m_wb_adr_o_LUT4_O_4_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(27) I2=sd_fifo_filler0.offset(27) I3=m_wb_adr_o_LUT4_O_5_I3 O=sd_fifo_filler0.wbm_adr_o(27)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(26) I2=sd_fifo_filler0.offset(26) I3=m_wb_adr_o_LUT4_O_6_I3 O=m_wb_adr_o_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(26) I2=sd_fifo_filler0.offset(26) I3=m_wb_adr_o_LUT4_O_6_I3 O=sd_fifo_filler0.wbm_adr_o(26)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(25) I1=dma_addr_reg_cross.out(25) I2=m_wb_adr_o_LUT4_O_7_I0 I3=m_wb_adr_o_LUT4_O_7_I1 O=m_wb_adr_o_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011101000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_7_I0 I1=m_wb_adr_o_LUT4_O_7_I1 I2=sd_fifo_filler0.offset(25) I3=dma_addr_reg_cross.out(25) O=sd_fifo_filler0.wbm_adr_o(25)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_9_I3 I1=sd_fifo_filler0.offset(23) I2=dma_addr_reg_cross.out(23) I3=m_wb_adr_o_LUT4_O_8_I3 O=m_wb_adr_o_LUT4_O_7_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(24) I3=sd_fifo_filler0.offset(24) O=m_wb_adr_o_LUT4_O_7_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=m_wb_adr_o_LUT4_O_9_I3 I1=sd_fifo_filler0.offset(23) I2=dma_addr_reg_cross.out(23) I3=m_wb_adr_o_LUT4_O_8_I3 O=sd_fifo_filler0.wbm_adr_o(24)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010000101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(24) I3=sd_fifo_filler0.offset(24) O=m_wb_adr_o_LUT4_O_8_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(23) I2=sd_fifo_filler0.offset(23) I3=m_wb_adr_o_LUT4_O_9_I3 O=sd_fifo_filler0.wbm_adr_o(23)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset(22) I1=m_wb_adr_o_LUT4_O_10_I1 I2=m_wb_adr_o_LUT4_O_10_I0 I3=dma_addr_reg_cross.out(22) O=m_wb_adr_o_LUT4_O_9_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101010011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_rx_fifo_o I2=sd_fifo_filler0.generic_fifo_dc_gray0.empty I3=m_wb_stb_o_LUT4_O_I2 O=sd_fifo_filler0.wbm_cyc_o
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00111010
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(31)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I0 I1=m_wb_dat_o_LUT4_O_1_I1 I2=m_wb_dat_o_LUT4_O_1_I2 I3=m_wb_dat_o_LUT4_O_1_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(30)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_10_I2 I3=m_wb_dat_o_LUT4_O_10_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(21)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_10_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](21) O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](21) O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_10_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](21) O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](21) O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_11_I0 I1=m_wb_dat_o_LUT4_O_11_I1 I2=m_wb_dat_o_LUT4_O_11_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(20)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_11_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_11_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](20) O=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](20) O=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_11_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](20) O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](20) O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_12_I2 I3=m_wb_dat_o_LUT4_O_12_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(19)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_12_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](19) O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](19) O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_12_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](19) O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](19) O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_13_I2 I3=m_wb_dat_o_LUT4_O_13_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(18)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_13_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](18) O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](18) O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_13_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](18) O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](18) O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_14_I2 I3=m_wb_dat_o_LUT4_O_14_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(17)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_14_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](17) O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](17) O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_14_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](17) O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](17) O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_15_I2 I3=m_wb_dat_o_LUT4_O_15_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(16)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_15_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](16) O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](16) O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_15_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](16) O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](16) O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_16_I2 I3=m_wb_dat_o_LUT4_O_16_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(15)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_16_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](15) O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](15) O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_16_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](15) O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](15) O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_17_I2 I3=m_wb_dat_o_LUT4_O_17_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(14)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_17_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](14) O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](14) O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_17_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](14) O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](14) O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I0 I1=m_wb_dat_o_LUT4_O_18_I1 I2=m_wb_dat_o_LUT4_O_18_I2 I3=m_wb_dat_o_LUT4_O_18_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(13)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_18_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](13) O=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](13) O=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_18_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_18_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](13) O=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](13) O=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_18_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_19_I2 I3=m_wb_dat_o_LUT4_O_19_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(12)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_19_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](12) O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](12) O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_19_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](12) O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](12) O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](30) O=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](30) O=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](30) O=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](30) O=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_2_I2 I3=m_wb_dat_o_LUT4_O_2_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(29)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_20_I0 I1=m_wb_dat_o_LUT4_O_20_I1 I2=m_wb_dat_o_LUT4_O_20_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(11)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_20_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_20_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](11) O=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](11) O=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_20_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](11) O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](11) O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_21_I2 I3=m_wb_dat_o_LUT4_O_21_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(10)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_21_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](10) O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](10) O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_21_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](10) O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](10) O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_22_I2 I3=m_wb_dat_o_LUT4_O_22_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(9)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_22_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](9) O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](9) O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_22_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](9) O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](9) O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I0 I1=m_wb_dat_o_LUT4_O_23_I1 I2=m_wb_dat_o_LUT4_O_23_I2 I3=m_wb_dat_o_LUT4_O_23_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(8)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_23_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](8) O=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](8) O=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_23_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_23_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](8) O=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](8) O=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_23_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_24_I2 I3=m_wb_dat_o_LUT4_O_24_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(7)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_24_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](7) O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](7) O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_24_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](7) O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](7) O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_25_I2 I3=m_wb_dat_o_LUT4_O_25_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(6)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_25_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](6) O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](6) O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_25_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](6) O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](6) O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I0 I1=m_wb_dat_o_LUT4_O_26_I1 I2=m_wb_dat_o_LUT4_O_26_I2 I3=m_wb_dat_o_LUT4_O_26_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_26_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](5) O=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](5) O=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_26_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_26_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](5) O=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](5) O=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_26_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_27_I0 I1=m_wb_dat_o_LUT4_O_27_I1 I2=m_wb_dat_o_LUT4_O_27_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_27_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_27_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](4) O=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](4) O=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_27_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](4) O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](4) O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_28_I2 I3=m_wb_dat_o_LUT4_O_28_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_28_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](3) O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](3) O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_28_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](3) O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](3) O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_29_I2 I3=m_wb_dat_o_LUT4_O_29_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_29_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](2) O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](2) O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_29_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](2) O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](2) O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_2_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](29) O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](29) O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](29) O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](29) O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_3_I0 I1=m_wb_dat_o_LUT4_O_3_I1 I2=m_wb_dat_o_LUT4_O_3_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(28)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I0 I1=m_wb_dat_o_LUT4_O_30_I1 I2=m_wb_dat_o_LUT4_O_30_I2 I3=m_wb_dat_o_LUT4_O_30_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_30_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](1) O=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](1) O=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_30_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_30_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](1) O=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](1) O=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_30_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_31_I2 I3=m_wb_dat_o_LUT4_O_31_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_31_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](0) O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](0) O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_31_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](0) O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](0) O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](28) O=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](28) O=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](28) O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](28) O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I0 I1=m_wb_dat_o_LUT4_O_4_I1 I2=m_wb_dat_o_LUT4_O_4_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(27)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_4_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](27) O=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](27) O=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_4_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](27) O=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](27) O=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_4_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](27) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](27) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](27) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](27) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](27) O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](27) O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_5_I2 I3=m_wb_dat_o_LUT4_O_5_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(26)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_5_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](26) O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](26) O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](26) O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](26) O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_6_I2 I3=m_wb_dat_o_LUT4_O_6_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(25)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_6_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](25) O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](25) O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_6_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](25) O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](25) O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_7_I0 I1=m_wb_dat_o_LUT4_O_7_I1 I2=m_wb_dat_o_LUT4_O_7_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(24)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_7_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_7_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](24) O=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](24) O=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_7_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](24) O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](24) O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_8_I2 I3=m_wb_dat_o_LUT4_O_8_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(23)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_8_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](23) O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](23) O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_8_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](23) O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](23) O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I0 I1=m_wb_dat_o_LUT4_O_9_I1 I2=m_wb_dat_o_LUT4_O_9_I2 I3=m_wb_dat_o_LUT4_O_9_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(22)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_9_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](22) O=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](22) O=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_9_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_9_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](22) O=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](22) O=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_9_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](31) O=m_wb_dat_o_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](31) O=m_wb_dat_o_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](31) O=m_wb_dat_o_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](31) O=m_wb_dat_o_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.wbm_ack_i I3=sd_fifo_filler0.wbm_stb_o O=m_wb_stb_o_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.empty I1=sd_fifo_filler0.fifo_rd_ack I2=m_wb_stb_o_LUT4_O_I2 I3=sd_data_master0.start_rx_fifo_o O=sd_fifo_filler0.wbm_stb_o
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100010011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.wbm_we_o I3=sd_fifo_filler0.wbm_ack_i O=m_wb_we_o_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10001111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I2=sd_fifo_filler0.wbm_ack_i I3=sd_fifo_filler0.wbm_we_o O=m_wb_we_o_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110000000000000
|
|
.subckt LUT4 I0=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) I3=m_wb_we_o_LUT4_I3_O O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001011000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 O=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) O=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.start_rx_fifo_o I3=sd_fifo_filler0.generic_fifo_dc_gray0.empty O=sd_fifo_filler0.wbm_we_o
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](31) D=response_0_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](30) D=response_0_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](21) D=response_0_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](20) D=response_0_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](19) D=response_0_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](18) D=response_0_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](17) D=response_0_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](16) D=response_0_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](15) D=response_0_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](14) D=response_0_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](13) D=response_0_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](12) D=response_0_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](29) D=response_0_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](11) D=response_0_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](10) D=response_0_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](9) D=response_0_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](8) D=response_0_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](7) D=response_0_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](6) D=response_0_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](5) D=response_0_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](4) D=response_0_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](3) D=response_0_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](2) D=response_0_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](28) D=response_0_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](1) D=response_0_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](0) D=response_0_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](27) D=response_0_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](26) D=response_0_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](25) D=response_0_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](24) D=response_0_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](23) D=response_0_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](22) D=response_0_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(31) D=response_0_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(30) D=response_0_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(21) D=response_0_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(20) D=response_0_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(19) D=response_0_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(18) D=response_0_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(17) D=response_0_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(16) D=response_0_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(15) D=response_0_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(14) D=response_0_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(13) D=response_0_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(12) D=response_0_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(29) D=response_0_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(11) D=response_0_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(10) D=response_0_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(9) D=response_0_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(8) D=response_0_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(7) D=response_0_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(6) D=response_0_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(5) D=response_0_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(4) D=response_0_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(3) D=response_0_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(2) D=response_0_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(28) D=response_0_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(1) D=response_0_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(0) D=response_0_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(27) D=response_0_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(26) D=response_0_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(25) D=response_0_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(24) D=response_0_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(23) D=response_0_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_0_reg_cross.out(22) D=response_0_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](31) D=response_1_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](30) D=response_1_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](21) D=response_1_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](20) D=response_1_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](19) D=response_1_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](18) D=response_1_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](17) D=response_1_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](16) D=response_1_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](15) D=response_1_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](14) D=response_1_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](13) D=response_1_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](12) D=response_1_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](29) D=response_1_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](11) D=response_1_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](10) D=response_1_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](9) D=response_1_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](8) D=response_1_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](7) D=response_1_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](6) D=response_1_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](5) D=response_1_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](4) D=response_1_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](3) D=response_1_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](2) D=response_1_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](28) D=response_1_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](1) D=response_1_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](0) D=response_1_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](27) D=response_1_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](26) D=response_1_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](25) D=response_1_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](24) D=response_1_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](23) D=response_1_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](22) D=response_1_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(31) D=response_1_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(30) D=response_1_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(21) D=response_1_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(20) D=response_1_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(19) D=response_1_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(18) D=response_1_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(17) D=response_1_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(16) D=response_1_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(15) D=response_1_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(14) D=response_1_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(13) D=response_1_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(12) D=response_1_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(29) D=response_1_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(11) D=response_1_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(10) D=response_1_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(9) D=response_1_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(8) D=response_1_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(7) D=response_1_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(6) D=response_1_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(5) D=response_1_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(4) D=response_1_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(3) D=response_1_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(2) D=response_1_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(28) D=response_1_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(1) D=response_1_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(0) D=response_1_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(27) D=response_1_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(26) D=response_1_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(25) D=response_1_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(24) D=response_1_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(23) D=response_1_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_1_reg_cross.out(22) D=response_1_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](31) D=response_2_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](30) D=response_2_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](21) D=response_2_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](20) D=response_2_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](19) D=response_2_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](18) D=response_2_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](17) D=response_2_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](16) D=response_2_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](15) D=response_2_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](14) D=response_2_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](13) D=response_2_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](12) D=response_2_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](29) D=response_2_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](11) D=response_2_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](10) D=response_2_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](9) D=response_2_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](8) D=response_2_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](7) D=response_2_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](6) D=response_2_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](5) D=response_2_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](4) D=response_2_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](3) D=response_2_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](2) D=response_2_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](28) D=response_2_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](1) D=response_2_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](0) D=response_2_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](27) D=response_2_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](26) D=response_2_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](25) D=response_2_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](24) D=response_2_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](23) D=response_2_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](22) D=response_2_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(31) D=response_2_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(30) D=response_2_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(21) D=response_2_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(20) D=response_2_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(19) D=response_2_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(18) D=response_2_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(17) D=response_2_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(16) D=response_2_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(15) D=response_2_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(14) D=response_2_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(13) D=response_2_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(12) D=response_2_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(29) D=response_2_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(11) D=response_2_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(10) D=response_2_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(9) D=response_2_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(8) D=response_2_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(7) D=response_2_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(6) D=response_2_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(5) D=response_2_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(4) D=response_2_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(3) D=response_2_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(2) D=response_2_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(28) D=response_2_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(1) D=response_2_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(0) D=response_2_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(27) D=response_2_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(26) D=response_2_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(25) D=response_2_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(24) D=response_2_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(23) D=response_2_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_2_reg_cross.out(22) D=response_2_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](31) D=response_3_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](30) D=response_3_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](21) D=response_3_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](20) D=response_3_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](19) D=response_3_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](18) D=response_3_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](17) D=response_3_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](16) D=response_3_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](15) D=response_3_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](14) D=response_3_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](13) D=response_3_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](12) D=response_3_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](29) D=response_3_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](11) D=response_3_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](10) D=response_3_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](9) D=response_3_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](8) D=response_3_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](7) D=response_3_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](6) D=response_3_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](5) D=response_3_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](4) D=response_3_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](3) D=response_3_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](2) D=response_3_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](28) D=response_3_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](1) D=response_3_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](0) D=response_3_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](27) D=response_3_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](26) D=response_3_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](25) D=response_3_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](24) D=response_3_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](23) D=response_3_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](22) D=response_3_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(31) D=response_3_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(30) D=response_3_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(21) D=response_3_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(20) D=response_3_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(19) D=response_3_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(18) D=response_3_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(17) D=response_3_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(16) D=response_3_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(15) D=response_3_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(14) D=response_3_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(13) D=response_3_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(12) D=response_3_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(29) D=response_3_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(11) D=response_3_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(10) D=response_3_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(9) D=response_3_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(8) D=response_3_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(7) D=response_3_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(6) D=response_3_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(5) D=response_3_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(4) D=response_3_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(3) D=response_3_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(2) D=response_3_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(28) D=response_3_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(1) D=response_3_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(0) D=response_3_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(27) D=response_3_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(26) D=response_3_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(25) D=response_3_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(24) D=response_3_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(23) D=response_3_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=response_3_reg_cross.out(22) D=response_3_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o I2=sd_cmd_master0.busy_check I3=sd_cmd_master0.go_idle_o O=sd_cmd_master0.next_state_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=sd_cmd_master0.busy_check D=command_reg_cross.out(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(39) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(38) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(29) D=argument_reg_cross.out(29) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(28) D=argument_reg_cross.out(28) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(27) D=argument_reg_cross.out(27) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(26) D=argument_reg_cross.out(26) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(25) D=argument_reg_cross.out(25) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(24) D=argument_reg_cross.out(24) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(23) D=argument_reg_cross.out(23) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(22) D=argument_reg_cross.out(22) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(21) D=argument_reg_cross.out(21) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(20) D=argument_reg_cross.out(20) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(37) D=command_reg_cross.out(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(19) D=argument_reg_cross.out(19) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(18) D=argument_reg_cross.out(18) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(17) D=argument_reg_cross.out(17) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(16) D=argument_reg_cross.out(16) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(15) D=argument_reg_cross.out(15) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(14) D=argument_reg_cross.out(14) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(13) D=argument_reg_cross.out(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(12) D=argument_reg_cross.out(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(11) D=argument_reg_cross.out(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(10) D=argument_reg_cross.out(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(36) D=command_reg_cross.out(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(9) D=argument_reg_cross.out(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(8) D=argument_reg_cross.out(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(7) D=argument_reg_cross.out(7) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(6) D=argument_reg_cross.out(6) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(5) D=argument_reg_cross.out(5) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(4) D=argument_reg_cross.out(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(3) D=argument_reg_cross.out(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(2) D=argument_reg_cross.out(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(1) D=argument_reg_cross.out(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(0) D=argument_reg_cross.out(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(35) D=command_reg_cross.out(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(34) D=command_reg_cross.out(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(33) D=command_reg_cross.out(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(32) D=command_reg_cross.out(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(31) D=argument_reg_cross.out(31) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd(30) D=argument_reg_cross.out(30) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_o I1=sd_cmd_master0.crc_check I2=sd_cmd_master0.crc_check_LUT4_I1_I2 I3=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN O=sd_cmd_master0.int_status_reg_ff_CQZ_1_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=cmd_serial_host0.crc_ok_o I1=sd_cmd_master0.crc_check I2=sd_cmd_master0.index_check_LUT4_I2_O I3=sd_cmd_master0.crc_check_LUT4_I1_1_I3 O=sd_cmd_master0.int_status_reg_ff_CQZ_3_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN_LUT4_O_I2 I2=cmd_serial_host0.finish_o I3=sd_cmd_master0.crc_check_LUT4_I1_I2 O=sd_cmd_master0.crc_check_LUT4_I1_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg_ff_CQZ_D I3=sd_cmd_master0.expect_response_LUT4_I3_I0 O=sd_cmd_master0.crc_check_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_cmd_master0.crc_check D=command_reg_cross.out(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0 I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=cmd_serial_host0.finish_o I3=sd_cmd_master0.expect_response O=sd_cmd_master0.expect_response_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I0 I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1 I2=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I2 I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(13) I1=sd_cmd_master0.watchdog(12) I2=sd_cmd_master0.timeout_reg(13) I3=sd_cmd_master0.timeout_reg(12) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000101010000
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_cmd_master0.watchdog(11) I2=sd_cmd_master0.timeout_reg(11) I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111011111111
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_cmd_master0.watchdog(10) I3=sd_cmd_master0.timeout_reg(10) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_cmd_master0.timeout_reg(8) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(7) I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_cmd_master0.timeout_reg(7) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010100011111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.watchdog(6) I3=sd_cmd_master0.timeout_reg(6) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_cmd_master0.watchdog(2) I2=sd_cmd_master0.timeout_reg(2) I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010110010
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(1) I1=sd_cmd_master0.timeout_reg(1) I2=sd_cmd_master0.timeout_reg(0) I3=sd_cmd_master0.watchdog(0) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.watchdog(3) I3=sd_cmd_master0.timeout_reg(3) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(3) I1=sd_cmd_master0.timeout_reg(3) I2=sd_cmd_master0.watchdog(4) I3=sd_cmd_master0.timeout_reg(4) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_cmd_master0.timeout_reg(4) I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.timeout_reg(5) I3=sd_cmd_master0.watchdog(5) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(5) I1=sd_cmd_master0.timeout_reg(5) I2=sd_cmd_master0.watchdog(6) I3=sd_cmd_master0.timeout_reg(6) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.timeout_reg(9) I3=sd_cmd_master0.watchdog(9) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.timeout_reg(9) I1=sd_cmd_master0.watchdog(9) I2=sd_cmd_master0.watchdog(10) I3=sd_cmd_master0.timeout_reg(10) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000000001011
|
|
.subckt LUT4 I0=sd_cmd_master0.timeout_reg(12) I1=sd_cmd_master0.watchdog(12) I2=sd_cmd_master0.timeout_reg(13) I3=sd_cmd_master0.watchdog(13) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(15) I1=sd_cmd_master0.timeout_reg(15) I2=sd_cmd_master0.timeout_reg(14) I3=sd_cmd_master0.watchdog(14) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(15) I1=sd_cmd_master0.watchdog(14) I2=sd_cmd_master0.timeout_reg(15) I3=sd_cmd_master0.timeout_reg(14) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt ff CQZ=sd_cmd_master0.expect_response D=sd_cmd_master0.expect_response_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=command_reg_cross.out(0) I3=command_reg_cross.out(1) O=sd_cmd_master0.expect_response_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=sd_cmd_master0.go_idle_o D=sd_cmd_master0.state(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.go_idle_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.state(0) I2=sd_cmd_master0.expect_response_LUT4_I3_I0 I3=sd_cmd_master0.state(1) O=sd_cmd_master0.go_idle_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.crc_check_LUT4_I1_I2 I2=sd_cmd_master0.index_check I3=cmd_serial_host0.index_ok_o O=sd_cmd_master0.index_check_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt ff CQZ=sd_cmd_master0.index_check D=command_reg_cross.out(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.int_status_reg(4) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.int_status_reg(3) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_1_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.int_status_reg(2) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN_LUT4_O_I2 I3=sd_cmd_master0.crc_check_LUT4_I1_I2 O=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=sd_cmd_master0.int_status_reg(1) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_3_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.int_status_reg(0) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.crc_check_LUT4_I1_1_I3 I2=sd_cmd_master0.int_status_reg_ff_CQZ_D I3=sd_cmd_master0.expect_response_LUT4_I3_I0 O=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN I3=sd_cmd_master0.index_check_LUT4_I2_O O=sd_cmd_master0.int_status_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_cmd_master0.long_response D=command_reg_cross.out(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_cmd_master0.next_state_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_reg(0) I2=sd_cmd_master0.state(1) I3=sd_cmd_master0.state(0) O=sd_cmd_master0.next_state(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000110000
|
|
.subckt LUT4 I0=sd_cmd_master0.go_idle_o I1=cmd_serial_host0.finish_o I2=sd_cmd_master0.next_state_LUT4_O_1_I2 I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.next_state(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000111110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_int_rst_cross.sync_clk_b(1) I2=cmd_int_rst_cross.sync_clk_b(2) I3=sd_cmd_master0.next_state_LUT4_O_1_I2 O=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_cmd_master0.state(0) I1=cmd_start_cross.sync_clk_b(2) I2=cmd_start_cross.sync_clk_b(1) I3=sd_cmd_master0.state(1) O=sd_cmd_master0.next_state_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111110
|
|
.subckt ff CQZ=response_0_reg_cross.in(31) D=cmd_response(119) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(30) D=cmd_response(118) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(21) D=cmd_response(109) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(20) D=cmd_response(108) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(19) D=cmd_response(107) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(18) D=cmd_response(106) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(17) D=cmd_response(105) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(16) D=cmd_response(104) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(15) D=cmd_response(103) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(14) D=cmd_response(102) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(13) D=cmd_response(101) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(12) D=cmd_response(100) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(29) D=cmd_response(117) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(11) D=cmd_response(99) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(10) D=cmd_response(98) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(9) D=cmd_response(97) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(8) D=cmd_response(96) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(7) D=cmd_response(95) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(6) D=cmd_response(94) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(5) D=cmd_response(93) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(4) D=cmd_response(92) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(3) D=cmd_response(91) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(2) D=cmd_response(90) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(28) D=cmd_response(116) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(1) D=cmd_response(89) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(0) D=cmd_response(88) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(27) D=cmd_response(115) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(26) D=cmd_response(114) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(25) D=cmd_response(113) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(24) D=cmd_response(112) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(23) D=cmd_response(111) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_0_reg_cross.in(22) D=cmd_response(110) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(31) D=cmd_response(87) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(30) D=cmd_response(86) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(21) D=cmd_response(77) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(20) D=cmd_response(76) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(19) D=cmd_response(75) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(18) D=cmd_response(74) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(17) D=cmd_response(73) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(16) D=cmd_response(72) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(15) D=cmd_response(71) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(14) D=cmd_response(70) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(13) D=cmd_response(69) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(12) D=cmd_response(68) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(29) D=cmd_response(85) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(11) D=cmd_response(67) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(10) D=cmd_response(66) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(9) D=cmd_response(65) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(8) D=cmd_response(64) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(7) D=cmd_response(63) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(6) D=cmd_response(62) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(5) D=cmd_response(61) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(4) D=cmd_response(60) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(3) D=cmd_response(59) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(2) D=cmd_response(58) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(28) D=cmd_response(84) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(1) D=cmd_response(57) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(0) D=cmd_response(56) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(27) D=cmd_response(83) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(26) D=cmd_response(82) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(25) D=cmd_response(81) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(24) D=cmd_response(80) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(23) D=cmd_response(79) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_1_reg_cross.in(22) D=cmd_response(78) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(31) D=cmd_response(55) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(30) D=cmd_response(54) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(21) D=cmd_response(45) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(20) D=cmd_response(44) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(19) D=cmd_response(43) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(18) D=cmd_response(42) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(17) D=cmd_response(41) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(16) D=cmd_response(40) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(15) D=cmd_response(39) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(14) D=cmd_response(38) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(13) D=cmd_response(37) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(12) D=cmd_response(36) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(29) D=cmd_response(53) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(11) D=cmd_response(35) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(10) D=cmd_response(34) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(9) D=cmd_response(33) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(8) D=cmd_response(32) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(7) D=cmd_response(31) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(6) D=cmd_response(30) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(5) D=cmd_response(29) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(4) D=cmd_response(28) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(3) D=cmd_response(27) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(2) D=cmd_response(26) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(28) D=cmd_response(52) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(1) D=cmd_response(25) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(0) D=cmd_response(24) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(27) D=cmd_response(51) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(26) D=cmd_response(50) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(25) D=cmd_response(49) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(24) D=cmd_response(48) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(23) D=cmd_response(47) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_2_reg_cross.in(22) D=cmd_response(46) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(31) D=cmd_response(23) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(30) D=cmd_response(22) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(21) D=cmd_response(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(20) D=cmd_response(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(19) D=cmd_response(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(18) D=cmd_response(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(17) D=cmd_response(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(16) D=cmd_response(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(15) D=cmd_response(7) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(14) D=cmd_response(6) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(13) D=cmd_response(5) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(12) D=cmd_response(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(29) D=cmd_response(21) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(11) D=cmd_response(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(10) D=cmd_response(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(9) D=cmd_response(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(8) D=cmd_response(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(7) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(6) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(5) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(4) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(3) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(2) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(28) D=cmd_response(20) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(1) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(0) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(27) D=cmd_response(19) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(26) D=cmd_response(18) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(25) D=cmd_response(17) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(24) D=cmd_response(16) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(23) D=cmd_response(15) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=response_3_reg_cross.in(22) D=cmd_response(14) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=software_reset_reg_cross.out I3=argument_reg_cross.rst O=sd_cmd_master0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=cmd_serial_host0.start_i D=sd_cmd_master0.start_xfr_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.start_xfr_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.state(1) I3=sd_cmd_master0.state(0) O=sd_cmd_master0.start_xfr_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=cmd_start_cross.sync_clk_b(2) I1=cmd_start_cross.sync_clk_b(1) I2=sd_cmd_master0.state(0) I3=sd_cmd_master0.state(1) O=sd_cmd_master0.start_xfr_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111111110110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.state(0) I3=sd_cmd_master0.state(1) O=sd_cmd_master0.next_state_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.state(1) I3=sd_cmd_master0.state(0) O=sd_cmd_master0.state_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.busy I3=sd_cmd_master0.state(1) O=sd_cmd_master0.watchdog_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01
|
|
.subckt ff CQZ=sd_cmd_master0.state(1) D=sd_cmd_master0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:147.1-155.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.state(0) D=sd_cmd_master0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:147.1-155.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(15) D=sd_cmd_master0.timeout_i(15) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(14) D=sd_cmd_master0.timeout_i(14) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(5) D=sd_cmd_master0.timeout_i(5) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(4) D=sd_cmd_master0.timeout_i(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(3) D=sd_cmd_master0.timeout_i(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(2) D=sd_cmd_master0.timeout_i(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(1) D=sd_cmd_master0.timeout_i(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(0) D=sd_cmd_master0.timeout_i(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(13) D=sd_cmd_master0.timeout_i(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(12) D=sd_cmd_master0.timeout_i(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(11) D=sd_cmd_master0.timeout_i(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(10) D=sd_cmd_master0.timeout_i(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(9) D=sd_cmd_master0.timeout_i(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(8) D=sd_cmd_master0.timeout_i(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(7) D=sd_cmd_master0.timeout_i(7) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_reg(6) D=sd_cmd_master0.timeout_i(6) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(15) D=sd_cmd_master0.watchdog_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(14) D=sd_cmd_master0.watchdog_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(5) D=sd_cmd_master0.watchdog_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.watchdog(5) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(4) D=sd_cmd_master0.watchdog_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(4) I3=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(0) I1=sd_cmd_master0.watchdog(1) I2=sd_cmd_master0.watchdog(2) I3=sd_cmd_master0.watchdog(3) O=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(3) D=sd_cmd_master0.watchdog_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_12_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(0) I1=sd_cmd_master0.watchdog(1) I2=sd_cmd_master0.watchdog(2) I3=sd_cmd_master0.watchdog(3) O=sd_cmd_master0.watchdog_ff_CQZ_12_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(2) D=sd_cmd_master0.watchdog_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(0) I1=sd_cmd_master0.watchdog(1) I2=sd_cmd_master0.watchdog(2) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(1) D=sd_cmd_master0.watchdog_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(1) I3=sd_cmd_master0.watchdog(0) O=sd_cmd_master0.watchdog_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(0) D=sd_cmd_master0.watchdog_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog(0) O=sd_cmd_master0.watchdog_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(13) I2=sd_cmd_master0.watchdog(14) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(13) D=sd_cmd_master0.watchdog_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(13) I3=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(10) I2=sd_cmd_master0.watchdog(11) I3=sd_cmd_master0.watchdog(12) O=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(12) D=sd_cmd_master0.watchdog_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_3_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(10) I2=sd_cmd_master0.watchdog(11) I3=sd_cmd_master0.watchdog(12) O=sd_cmd_master0.watchdog_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(11) D=sd_cmd_master0.watchdog_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(10) I2=sd_cmd_master0.watchdog(11) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(10) D=sd_cmd_master0.watchdog_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(10) I3=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(7) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.watchdog(9) O=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(9) D=sd_cmd_master0.watchdog_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_6_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(7) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.watchdog(9) O=sd_cmd_master0.watchdog_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(8) D=sd_cmd_master0.watchdog_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(7) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(7) D=sd_cmd_master0.watchdog_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(7) I3=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.watchdog(5) I3=sd_cmd_master0.watchdog(6) O=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_cmd_master0.watchdog(6) D=sd_cmd_master0.watchdog_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_9_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.watchdog(5) I3=sd_cmd_master0.watchdog(6) O=sd_cmd_master0.watchdog_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_cmd_master0.watchdog(13) I1=sd_cmd_master0.watchdog(14) I2=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3 I3=sd_cmd_master0.watchdog(15) O=sd_cmd_master0.watchdog_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111110000000
|
|
.subckt ff CQZ=argument_reg_cross.in(31) D=sd_controller_wb0.wb_dat_i(31) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(30) D=sd_controller_wb0.wb_dat_i(30) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(21) D=sd_controller_wb0.wb_dat_i(21) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(20) D=sd_controller_wb0.wb_dat_i(20) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(19) D=sd_controller_wb0.wb_dat_i(19) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(18) D=sd_controller_wb0.wb_dat_i(18) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(17) D=sd_controller_wb0.wb_dat_i(17) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(16) D=sd_controller_wb0.wb_dat_i(16) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(29) D=sd_controller_wb0.wb_dat_i(29) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(28) D=sd_controller_wb0.wb_dat_i(28) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(27) D=sd_controller_wb0.wb_dat_i(27) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(26) D=sd_controller_wb0.wb_dat_i(26) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(25) D=sd_controller_wb0.wb_dat_i(25) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(24) D=sd_controller_wb0.wb_dat_i(24) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(23) D=sd_controller_wb0.wb_dat_i(23) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=argument_reg_cross.in(22) D=sd_controller_wb0.wb_dat_i(22) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_count_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=argument_reg_cross.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=block_size_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=clock_divider_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_int_enable_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_int_enable_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_int_enable_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_int_enable_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_int_enable_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=cmd_int_rst_edge.sig D=sd_controller_wb0.cmd_int_rst_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.cmd_int_rst_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=cmd_start_edge.sig D=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=command_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=command_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=controll_setting_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_int_enable_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_int_enable_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_int_enable_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(2) I1=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=wb_we_i_LUT4_I2_O O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_adr_i(5) O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.wb_adr_i(2) O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(6) I2=sd_controller_wb0.wb_adr_i(7) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=data_int_rst_edge.sig D=sd_controller_wb0.data_int_rst_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O O=sd_controller_wb0.data_int_rst_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(31) D=sd_controller_wb0.wb_dat_i(31) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(30) D=sd_controller_wb0.wb_dat_i(30) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(21) D=sd_controller_wb0.wb_dat_i(21) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(20) D=sd_controller_wb0.wb_dat_i(20) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(19) D=sd_controller_wb0.wb_dat_i(19) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(18) D=sd_controller_wb0.wb_dat_i(18) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(17) D=sd_controller_wb0.wb_dat_i(17) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(16) D=sd_controller_wb0.wb_dat_i(16) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(29) D=sd_controller_wb0.wb_dat_i(29) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(28) D=sd_controller_wb0.wb_dat_i(28) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(27) D=sd_controller_wb0.wb_dat_i(27) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(26) D=sd_controller_wb0.wb_dat_i(26) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(25) D=sd_controller_wb0.wb_dat_i(25) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(24) D=sd_controller_wb0.wb_dat_i(24) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(23) D=sd_controller_wb0.wb_dat_i(23) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=dma_addr_reg_cross.in(22) D=sd_controller_wb0.wb_dat_i(22) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O I2=sd_controller_wb0.software_reset_reg I3=sd_controller_wb0.timeout_reg(0) O=sd_controller_wb0.software_reset_reg_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=cmd_int_status_reg_cross.out(0) I3=sd_controller_wb0.software_reset_reg_LUT4_I2_O O=sd_controller_wb0.software_reset_reg_LUT4_I2_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00111010
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_LUT4_I2_O_LUT4_I3_O I1=cmd_int_enable_reg_cross.in(0) I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100001010
|
|
.subckt ff CQZ=sd_controller_wb0.software_reset_reg D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2 I3=wb_we_i_LUT4_I2_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.wb_adr_i(2) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2 I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(5) I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2 O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(5) I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(7) I3=sd_controller_wb0.wb_adr_i(6) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(4) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O O=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(3) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_adr_i(2) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.timeout_reg(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.wb_ack_o D=sd_controller_wb0.wb_ack_o_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_I3 QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(31) D=sd_controller_wb0.wb_dat_o_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(30) D=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(21) D=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(21) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(21) I1=response_2_reg_cross.out(21) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(21) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(21) I3=response_1_reg_cross.out(21) O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(20) D=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(20) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(20) I1=response_2_reg_cross.out(20) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(20) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(20) I3=response_1_reg_cross.out(20) O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(19) D=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(19) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(19) I1=response_2_reg_cross.out(19) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(19) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(19) I3=response_1_reg_cross.out(19) O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(18) D=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(18) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(18) I1=response_2_reg_cross.out(18) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(18) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(18) I3=response_1_reg_cross.out(18) O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(17) D=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(17) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(17) I1=response_2_reg_cross.out(17) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(17) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(17) I3=response_1_reg_cross.out(17) O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(16) D=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(16) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(16) I1=response_2_reg_cross.out(16) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(16) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(16) I3=response_1_reg_cross.out(16) O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(15) D=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(15) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=controll_setting_reg_cross.in(15) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=response_2_reg_cross.out(15) I3=response_3_reg_cross.out(15) O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(15) I2=sd_controller_wb0.timeout_reg(15) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(15) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(15) I3=response_1_reg_cross.out(15) O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(14) D=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(14) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=controll_setting_reg_cross.in(14) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=response_2_reg_cross.out(14) I3=response_3_reg_cross.out(14) O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(14) I2=sd_controller_wb0.timeout_reg(14) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(14) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(14) I3=response_1_reg_cross.out(14) O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(13) D=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000011111111
|
|
.subckt LUT4 I0=response_1_reg_cross.out(13) I1=response_0_reg_cross.out(13) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=command_reg_cross.in(13) I1=argument_reg_cross.in(13) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(13) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=controll_setting_reg_cross.in(13) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=response_2_reg_cross.out(13) I3=response_3_reg_cross.out(13) O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(13) I2=sd_controller_wb0.timeout_reg(13) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(12) D=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000011111111
|
|
.subckt LUT4 I0=response_1_reg_cross.out(12) I1=response_0_reg_cross.out(12) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=command_reg_cross.in(12) I1=argument_reg_cross.in(12) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(12) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=controll_setting_reg_cross.in(12) I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100000000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(12) I1=response_2_reg_cross.out(12) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(12) I2=sd_controller_wb0.timeout_reg(12) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(30) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(30) I1=response_2_reg_cross.out(30) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(30) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(30) I3=response_1_reg_cross.out(30) O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(29) D=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(11) D=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(11) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(11) I1=response_0_reg_cross.out(11) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=command_reg_cross.in(11) I1=argument_reg_cross.in(11) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(11) I1=response_2_reg_cross.out(11) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(11) I2=block_size_reg_cross.in(11) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(11) I2=sd_controller_wb0.timeout_reg(11) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(10) D=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(10) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(10) I1=response_0_reg_cross.out(10) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=command_reg_cross.in(10) I1=argument_reg_cross.in(10) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(10) I1=response_2_reg_cross.out(10) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(10) I2=block_size_reg_cross.in(10) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(10) I2=sd_controller_wb0.timeout_reg(10) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(9) D=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(9) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(9) I1=response_0_reg_cross.out(9) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=command_reg_cross.in(9) I1=argument_reg_cross.in(9) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(9) I1=response_2_reg_cross.out(9) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(9) I2=block_size_reg_cross.in(9) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(9) I2=sd_controller_wb0.timeout_reg(9) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(8) D=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(8) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(8) I1=response_0_reg_cross.out(8) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=command_reg_cross.in(8) I1=argument_reg_cross.in(8) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(8) I1=response_2_reg_cross.out(8) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(8) I2=block_size_reg_cross.in(8) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(8) I2=sd_controller_wb0.timeout_reg(8) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(7) D=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(7) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(7) I1=response_2_reg_cross.out(7) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(7) I2=block_size_reg_cross.in(7) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(7) I1=response_0_reg_cross.out(7) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=command_reg_cross.in(7) I1=argument_reg_cross.in(7) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I1 I2=block_count_reg_cross.in(7) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I1=clock_divider_reg_cross.in(7) I2=sd_controller_wb0.timeout_reg(7) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(6) D=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(6) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(6) I1=response_0_reg_cross.out(6) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=command_reg_cross.in(6) I1=argument_reg_cross.in(6) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(6) I1=response_2_reg_cross.out(6) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(6) I2=block_size_reg_cross.in(6) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.timeout_reg(6) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(6) I2=clock_divider_reg_cross.in(6) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(5) D=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(5) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(5) I1=response_2_reg_cross.out(5) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(5) I2=block_size_reg_cross.in(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(5) I1=response_0_reg_cross.out(5) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=command_reg_cross.in(5) I1=argument_reg_cross.in(5) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3_LUT4_O_I1 I2=block_count_reg_cross.in(5) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I1=clock_divider_reg_cross.in(5) I2=sd_controller_wb0.timeout_reg(5) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(4) D=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(4) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(4) I2=clock_divider_reg_cross.in(4) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=dma_addr_reg_cross.in(4) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O I1=sd_controller_wb0.timeout_reg(4) I2=cmd_int_status_reg_cross.out(4) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(4) I1=response_2_reg_cross.out(4) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(4) I2=block_size_reg_cross.in(4) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I2=argument_reg_cross.in(4) I3=command_reg_cross.in(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(4) I3=response_1_reg_cross.out(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(3) D=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=cmd_int_status_reg_cross.out(3) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(3) I2=sd_controller_wb0.timeout_reg(3) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=dma_addr_reg_cross.in(3) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(3) I2=clock_divider_reg_cross.in(3) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(3) I1=response_2_reg_cross.out(3) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(3) I2=block_size_reg_cross.in(3) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I2=argument_reg_cross.in(3) I3=command_reg_cross.in(3) O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(3) I3=response_1_reg_cross.out(3) O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(2) D=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111111111111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=response_1_reg_cross.out(2) I1=response_0_reg_cross.out(2) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=command_reg_cross.in(2) I1=argument_reg_cross.in(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(2) I1=response_2_reg_cross.out(2) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(2) I2=block_size_reg_cross.in(2) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1 I2=clock_divider_reg_cross.in(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cmd_int_status_reg_cross.out(2) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=dma_addr_reg_cross.in(2) I1=data_int_enable_reg_cross.in(2) I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(2) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=data_int_status_reg_cross.out(2) O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(2) I2=sd_controller_wb0.timeout_reg(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(29) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(29) I1=response_2_reg_cross.out(29) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(29) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(29) I3=response_1_reg_cross.out(29) O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(28) D=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(1) D=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(1) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111000000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(1) I2=clock_divider_reg_cross.in(1) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O I1=sd_controller_wb0.timeout_reg(1) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=dma_addr_reg_cross.in(1) I1=data_int_enable_reg_cross.in(1) I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I1=data_int_status_reg_cross.out(1) I2=cmd_int_status_reg_cross.out(1) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=response_3_reg_cross.out(1) I1=response_2_reg_cross.out(1) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(1) I2=block_size_reg_cross.in(1) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I2=argument_reg_cross.in(1) I3=command_reg_cross.in(1) O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(1) I3=response_1_reg_cross.out(1) O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(0) D=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000100001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0 I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2 I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(5) I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(3) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2 I3=block_size_reg_cross.in(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01011100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=controll_setting_reg_cross.in(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01011100
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000001000100
|
|
.subckt LUT4 I0=command_reg_cross.in(0) I1=argument_reg_cross.in(0) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=response_0_reg_cross.out(0) I1=response_1_reg_cross.out(0) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010111111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_3_reg_cross.out(0) I3=response_2_reg_cross.out(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 00110101
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=clock_divider_reg_cross.in(0) I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=dma_addr_reg_cross.in(0) I1=data_int_enable_reg_cross.in(0) I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(0) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=data_int_status_reg_cross.out(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(28) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(28) I1=response_2_reg_cross.out(28) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(28) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(28) I3=response_1_reg_cross.out(28) O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(27) D=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(27) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(27) I1=response_2_reg_cross.out(27) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(27) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(27) I3=response_1_reg_cross.out(27) O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(26) D=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(26) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(26) I1=response_2_reg_cross.out(26) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(26) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(26) I3=response_1_reg_cross.out(26) O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(25) D=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(25) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(25) I1=response_2_reg_cross.out(25) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(25) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(25) I3=response_1_reg_cross.out(25) O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(24) D=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(24) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(24) I1=response_2_reg_cross.out(24) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(24) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(24) I3=response_1_reg_cross.out(24) O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(23) D=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(23) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(23) I1=response_2_reg_cross.out(23) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(23) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(23) I3=response_1_reg_cross.out(23) O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_controller_wb0.wb_dat_o(22) D=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(22) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(22) I1=response_2_reg_cross.out(22) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(22) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(22) I3=response_1_reg_cross.out(22) O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(31) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=response_3_reg_cross.out(31) I1=response_2_reg_cross.out(31) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(31) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(31) I3=response_1_reg_cross.out(31) O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.d_write_o I3=sd_data_master0.d_read_o O=sd_data_serial_host0.next_state_LUT4_O_5_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_data_master0.d_read_o D=sd_data_master0.d_read_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.d_read_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.next_state_LUT4_O_1_I3 I3=sd_data_master0.d_read_o_ff_CQZ_D_LUT4_O_I3 O=sd_data_master0.d_read_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.state(0) I2=sd_data_master0.state(1) I3=sd_data_master0.state(2) O=sd_data_master0.d_read_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt ff CQZ=sd_data_master0.d_write_o D=sd_data_master0.d_write_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.d_write_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.tx_cycle_ff_CQZ_D I3=sd_data_master0.d_read_o_ff_CQZ_D_LUT4_O_I3 O=sd_data_master0.d_write_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=data_int_status_reg_cross.in(2) D=sd_data_master0.int_status_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.int_status_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_int_status_reg_cross.in(1) D=sd_data_master0.trans_done_LUT4_I3_I1 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.int_status_o_ff_CQZ_1_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_int_status_reg_cross.in(0) D=sd_data_master0.trans_done_LUT4_I3_I1 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.int_status_o_ff_CQZ_2_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.trans_done_LUT4_I3_I1 I3=sd_data_master0.tx_cycle_LUT4_I2_O O=sd_data_master0.int_status_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.next_state_LUT4_O_I2 I3=sd_data_master0.next_state_LUT4_O_I3 O=sd_data_master0.next_state(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.next_state_LUT4_O_1_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_master0.next_state_LUT4_O_1_I3 O=sd_data_master0.next_state(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.state(1) I2=sd_data_master0.state(2) I3=sd_data_master0.state(0) O=sd_data_master0.next_state_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_master0.state(0) I1=sd_data_master0.start_tx_i I2=sd_data_master0.next_state_LUT4_O_I3 I3=sd_data_master0.next_state_LUT4_O_2_I3 O=sd_data_master0.next_state(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.state(1) I3=sd_data_master0.state(2) O=sd_data_master0.next_state_LUT4_O_2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.start_rx_fifo_o I3=sd_data_master0.start_tx_fifo_o O=sd_fifo_filler0.offset_ff_CQZ_31_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=sd_data_master0.start_rx_fifo_o D=sd_data_master0.next_state_LUT4_O_2_I3 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.tx_cycle_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I1=sd_data_master0.start_tx_fifo_o I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=m_wb_stb_o_LUT4_I3_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_data_master0.start_tx_fifo_o I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=m_wb_stb_o_LUT4_I3_O I1=sd_data_master0.start_tx_fifo_o I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I1_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I1_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I2=m_wb_stb_o_LUT4_I3_O I3=sd_data_master0.start_tx_fifo_o O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=m_wb_stb_o_LUT4_I3_O I3=sd_data_master0.start_tx_fifo_o O=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I3_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I3_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I3_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I3_O O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_data_master0.start_tx_fifo_o D=sd_data_master0.tx_cycle_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.tx_cycle_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_master0.state(2) D=sd_data_master0.next_state(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:121.1-129.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_master0.state(1) D=sd_data_master0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:121.1-129.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_master0.state(0) D=sd_data_master0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:121.1-129.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.trans_done_LUT4_I3_I1 I2=data_int_status_reg_cross.in(2) I3=sd_data_master0.trans_done O=sd_data_master0.int_status_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.tx_cycle_LUT4_I2_I3 I3=sd_data_master0.trans_done O=sd_data_master0.next_state_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_master0.trans_done D=sd_data_master0.tx_cycle_LUT4_I2_I3 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.trans_done_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I1=sd_data_master0.tx_cycle_LUT4_I2_1_O I2=sd_data_master0.state(0) I3=sd_data_master0.state(1) O=sd_data_master0.trans_done_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=sd_data_master0.tx_fifo_empty_i I1=sd_data_master0.rx_fifo_full_i I2=sd_data_master0.tx_cycle I3=sd_data_master0.tx_cycle_LUT4_I2_I3 O=sd_data_master0.tx_cycle_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_master0.tx_fifo_empty_i I1=sd_data_master0.rx_fifo_full_i I2=sd_data_master0.tx_cycle I3=sd_data_master0.tx_cycle_LUT4_I2_I3 O=sd_data_master0.tx_cycle_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.state(2) I2=sd_data_master0.state(1) I3=sd_data_master0.state(0) O=sd_data_master0.tx_cycle_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.tx_cycle_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_master0.d_read_o_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_master0.tx_cycle D=sd_data_master0.tx_cycle_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.tx_cycle_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.state(0) I3=sd_data_master0.next_state_LUT4_O_2_I3 O=sd_data_master0.tx_cycle_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.next_state_LUT4_O_2_I3 I3=sd_data_master0.next_state_LUT4_O_1_I3 O=sd_data_master0.tx_cycle_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000000010001
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010001000100
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010001000100
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(3) O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010001000100
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(3) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(2) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0 I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011101011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din(2) I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(2) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(10) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(6) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(14) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(1) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0 I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011101011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din(1) I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111100010001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_c(0) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001111101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_c(2) I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(3) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(11) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(10) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(2) I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.crc_c(3) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(14) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(6) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(0) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.last_din(0) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(2) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(10) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(6) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(14) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.crc_c(3) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0 I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011101011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din(3) I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(11) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(3) I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(2) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(10) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(6) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(14) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(3) D=sd_data_serial_host0.DAT_dat_i(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(2) D=sd_data_serial_host0.DAT_dat_i(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(1) D=sd_data_serial_host0.DAT_dat_i(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(0) D=sd_data_serial_host0.DAT_dat_i(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_data_serial_host0.DAT_oe_o D=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011101111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I1=sd_data_serial_host0.data_cycles(8) I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.data_cycles(9) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011101111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.transf_cnt(14) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011101110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110001100111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(14) I1=sd_data_serial_host0.transf_cnt(15) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100001000100001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(15) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111101100001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.transf_cnt(10) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.transf_cnt(8) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(6) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 I3=sd_data_serial_host0.data_cycles(6) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110001100111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(10) I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.data_cycles(10) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100001000001101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(11) I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(15) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101010011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000101011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(8) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010101110110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(7) I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.transf_cnt(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.data_cycles(11) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.transf_cnt(13) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.rd_ff_CQZ_QEN I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(15) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(14) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(5) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(5) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(4) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(5) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(4) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=block_count_reg_cross.out(4) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(4) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101000111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(2) I1=sd_data_serial_host0.blkcnt_reg(1) I2=sd_data_serial_host0.blkcnt_reg(3) I3=sd_data_serial_host0.blkcnt_reg(0) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(3) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D_LUT4_O_I2 I3=block_count_reg_cross.out(3) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(2) I1=sd_data_serial_host0.blkcnt_reg(1) I2=sd_data_serial_host0.blkcnt_reg(0) I3=sd_data_serial_host0.blkcnt_reg(3) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000001
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(2) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D_LUT4_O_I2 I3=block_count_reg_cross.out(2) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg(2) I2=sd_data_serial_host0.blkcnt_reg(0) I3=sd_data_serial_host0.blkcnt_reg(1) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100001
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(1) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=block_count_reg_cross.out(1) I1=sd_data_serial_host0.blkcnt_reg(1) I2=sd_data_serial_host0.blkcnt_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101011000011
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(0) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg(0) I3=block_count_reg_cross.out(0) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=block_count_reg_cross.out(14) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(14) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101000111100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(13) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=block_count_reg_cross.out(13) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(13) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101000111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D_LUT4_O_I1 I3=sd_data_serial_host0.blkcnt_reg(13) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(12) I1=sd_data_serial_host0.blkcnt_reg(10) I2=sd_data_serial_host0.blkcnt_reg(11) I3=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(12) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D_LUT4_O_I2 I3=block_count_reg_cross.out(12) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(10) I1=sd_data_serial_host0.blkcnt_reg(11) I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 I3=sd_data_serial_host0.blkcnt_reg(12) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100010000
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(11) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(11) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(10) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(11) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(10) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=block_count_reg_cross.out(10) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(10) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101000111100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(9) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D_LUT4_O_I2 I3=block_count_reg_cross.out(9) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(8) I1=sd_data_serial_host0.blkcnt_reg(7) I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(9) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100010000
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(8) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(8) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(7) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(8) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(7) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=block_count_reg_cross.out(7) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg(7) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101000111100
|
|
.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(6) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(6) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(6) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.blkcnt_reg(6) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(8) I1=sd_data_serial_host0.blkcnt_reg(9) I2=sd_data_serial_host0.blkcnt_reg(7) I3=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.blkcnt_reg(5) I3=sd_data_serial_host0.blkcnt_reg(4) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(15) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(14) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(15) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000100
|
|
.subckt ff CQZ=sd_data_serial_host0.bus_4bit D=controll_setting_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:394.29-394.143|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.bus_4bit_reg D=sd_data_serial_host0.bus_4bit QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.busy_int D=sd_data_serial_host0.busy_int_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.busy_int_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.busy_int_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.busy_int_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_c(4) D=sd_data_serial_host0.crc_c_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_c(3) D=sd_data_serial_host0.crc_c_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.crc_c_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_c(2) D=sd_data_serial_host0.crc_c_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.crc_c_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100001
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_c(1) D=sd_data_serial_host0.crc_c_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.crc_c(0) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 O=sd_data_serial_host0.crc_c_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101011
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_c(0) D=sd_data_serial_host0.crc_c_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.crc_c_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I1=sd_data_serial_host0.state(4) I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c(4) O=sd_data_serial_host0.crc_c_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010101110111010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.crc_c(3) O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE D=sd_data_serial_host0.crc_en_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_en_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.crc_en_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O I2=sd_data_serial_host0.crc_c(4) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_master0.crc_ok_i I1=sd_data_master0.next_state_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_master0.trans_done_LUT4_I3_I1 O=sd_data_master0.int_status_o_ff_CQZ_1_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I1=sd_data_master0.crc_ok_i I2=sd_data_master0.next_state_LUT4_O_I2 I3=sd_data_master0.trans_done_LUT4_I3_I1 O=sd_data_master0.int_status_o_ff_CQZ_2_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000011111111
|
|
.subckt ff CQZ=sd_data_master0.crc_ok_i D=sd_data_serial_host0.crc_ok_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_s(0) I1=sd_data_serial_host0.crc_s(2) I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=sd_data_serial_host0.crc_s(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101110111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din(2) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din(1) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_c(0) I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din(0) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111110110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111111101110
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(11) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(3) I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I1 I1=sd_data_serial_host0.transf_cnt(7) I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I0 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_I2_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(8) I3=sd_data_serial_host0.transf_cnt(9) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000110000010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.transf_cnt(12) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.transf_cnt(10) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.data_cycles(11) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.transf_cnt(8) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011001010100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=sd_data_serial_host0.transf_cnt(11) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001011101110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10100011
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.transf_cnt(6) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.data_cycles(4) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I2_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100000011001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.data_cycles(5) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100100010110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.transf_cnt(5) I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111011010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(1) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(3) I1=sd_data_serial_host0.transf_cnt(2) I2=sd_data_serial_host0.data_cycles(3) I3=sd_data_serial_host0.data_cycles(2) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(2) I1=sd_data_serial_host0.data_cycles(2) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR D=sd_data_serial_host0.crc_rst_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_rst_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_cmd_master0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 O=sd_data_serial_host0.crc_rst_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.busy_int I2=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.next_block_ff_CQZ_QEN O=sd_data_serial_host0.crc_rst_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_s(2) D=sd_data_serial_host0.crc_s_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_s_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_s(1) D=sd_data_serial_host0.crc_s_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_s_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=sd_data_serial_host0.crc_s(1) I2=sd_data_serial_host0.crc_s_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_s_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(0) I2=sd_data_serial_host0.crc_status(2) I3=sd_data_serial_host0.crc_status(1) O=sd_data_serial_host0.crc_s_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_s(0) D=sd_data_serial_host0.crc_s_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_s_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=sd_data_serial_host0.crc_s(0) I2=sd_data_serial_host0.crc_s_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_s_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(2) I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_s_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=sd_data_serial_host0.crc_s(2) I2=sd_data_serial_host0.crc_s_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_s_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(1) I2=sd_data_serial_host0.crc_status(2) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_s_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_serial_host0.crc_s_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.crc_s_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(2) I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_s_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_status(2) D=sd_data_serial_host0.crc_status_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_status_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_status(1) D=sd_data_serial_host0.crc_status_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_status_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_status_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.crc_status(0) D=sd_data_serial_host0.crc_status_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_status_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_status_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_status(0) I1=sd_data_serial_host0.crc_status(1) I2=sd_data_serial_host0.crc_status(2) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_status_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.crc_status_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111111101110
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(14) D=sd_data_serial_host0.data_cycles_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(13) D=sd_data_serial_host0.data_cycles_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(4) D=sd_data_serial_host0.data_cycles_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(1) I3=block_size_reg_cross.out(3) O=sd_data_serial_host0.data_cycles_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(3) D=sd_data_serial_host0.data_cycles_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(2) I3=block_size_reg_cross.out(0) O=sd_data_serial_host0.data_cycles_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(2) D=sd_data_serial_host0.data_cycles_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=block_size_reg_cross.out(1) I3=sd_data_serial_host0.bus_4bit O=sd_data_serial_host0.data_cycles_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(1) D=sd_data_serial_host0.data_cycles_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.bus_4bit I3=block_size_reg_cross.out(0) O=sd_data_serial_host0.data_cycles_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(0) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=block_size_reg_cross.out(10) I3=sd_data_serial_host0.bus_4bit O=sd_data_serial_host0.data_cycles_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(12) D=sd_data_serial_host0.data_cycles_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(9) I3=block_size_reg_cross.out(11) O=sd_data_serial_host0.data_cycles_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(11) D=sd_data_serial_host0.data_cycles_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(8) I3=block_size_reg_cross.out(10) O=sd_data_serial_host0.data_cycles_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(10) D=sd_data_serial_host0.data_cycles_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(7) I3=block_size_reg_cross.out(9) O=sd_data_serial_host0.data_cycles_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(9) D=sd_data_serial_host0.data_cycles_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(6) I3=block_size_reg_cross.out(8) O=sd_data_serial_host0.data_cycles_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(8) D=sd_data_serial_host0.data_cycles_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(5) I3=block_size_reg_cross.out(7) O=sd_data_serial_host0.data_cycles_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(7) D=sd_data_serial_host0.data_cycles_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(4) I3=block_size_reg_cross.out(6) O=sd_data_serial_host0.data_cycles_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(6) D=sd_data_serial_host0.data_cycles_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(3) I3=block_size_reg_cross.out(5) O=sd_data_serial_host0.data_cycles_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_cycles(5) D=sd_data_serial_host0.data_cycles_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(2) I3=block_size_reg_cross.out(4) O=sd_data_serial_host0.data_cycles_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=block_size_reg_cross.out(11) I3=sd_data_serial_host0.bus_4bit O=sd_data_serial_host0.data_cycles_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=data_in_rx_fifo(31) D=sd_data_serial_host0.data_out_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_in_rx_fifo(30) D=sd_data_serial_host0.data_out_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_in_rx_fifo(21) D=sd_data_serial_host0.data_out_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(21) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(21) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(20) D=sd_data_serial_host0.data_out_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(20) O=sd_data_serial_host0.data_out_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=data_in_rx_fifo(19) D=sd_data_serial_host0.data_out_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(19) I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(19) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(18) D=sd_data_serial_host0.data_out_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(18) I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(18) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(17) D=sd_data_serial_host0.data_out_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(17) I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(1) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(17) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(16) D=sd_data_serial_host0.data_out_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(16) O=sd_data_serial_host0.data_out_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=data_in_rx_fifo(15) D=sd_data_serial_host0.data_out_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(15) I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(15) I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(14) D=sd_data_serial_host0.data_out_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I2=data_in_rx_fifo(14) I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(14) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt ff CQZ=data_in_rx_fifo(13) D=sd_data_serial_host0.data_out_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I2=data_in_rx_fifo(13) I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(2) I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(13) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=data_in_rx_fifo(12) D=sd_data_serial_host0.data_out_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(12) O=sd_data_serial_host0.data_out_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I3=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=data_in_rx_fifo(30) I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(30) I2=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(13) I1=sd_data_serial_host0.transf_cnt(14) I2=sd_data_serial_host0.transf_cnt(15) I3=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(5) I1=sd_data_serial_host0.transf_cnt(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.transf_cnt(8) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(9) I1=sd_data_serial_host0.transf_cnt(10) I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.transf_cnt(12) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.transf_cnt(2) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)"
|
|
.param INIT 0000000000000001
|
|
.subckt ff CQZ=data_in_rx_fifo(29) D=sd_data_serial_host0.data_out_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_in_rx_fifo(11) D=sd_data_serial_host0.data_out_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(11) I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(11) I2=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(10) D=sd_data_serial_host0.data_out_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(10) I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(10) I2=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(9) D=sd_data_serial_host0.data_out_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(9) I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(9) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(8) D=sd_data_serial_host0.data_out_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(8) O=sd_data_serial_host0.data_out_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt ff CQZ=data_in_rx_fifo(7) D=sd_data_serial_host0.data_out_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(7) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(7) I2=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(6) D=sd_data_serial_host0.data_out_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(6) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(6) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt ff CQZ=data_in_rx_fifo(5) D=sd_data_serial_host0.data_out_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(5) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(5) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=data_in_rx_fifo(4) D=sd_data_serial_host0.data_out_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(4) O=sd_data_serial_host0.data_out_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=data_in_rx_fifo(3) D=sd_data_serial_host0.data_out_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(3) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(3) I2=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 O=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=data_in_rx_fifo(2) D=sd_data_serial_host0.data_out_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(2) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(2) I2=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=data_in_rx_fifo(29) I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I1 I2=data_in_rx_fifo(29) I3=sd_data_serial_host0.DAT_dat_reg(0) O=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=data_in_rx_fifo(28) D=sd_data_serial_host0.data_out_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=data_in_rx_fifo(1) D=sd_data_serial_host0.data_out_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_30_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(1) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(1) I2=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=data_in_rx_fifo(0) D=sd_data_serial_host0.data_out_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_31_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(0) O=sd_data_serial_host0.data_out_ff_CQZ_31_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_31_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(28) O=sd_data_serial_host0.data_out_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=data_in_rx_fifo(27) D=sd_data_serial_host0.data_out_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(27) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(27) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=data_in_rx_fifo(26) D=sd_data_serial_host0.data_out_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(26) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(26) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=data_in_rx_fifo(25) D=sd_data_serial_host0.data_out_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(25) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(25) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=data_in_rx_fifo(24) D=sd_data_serial_host0.data_out_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(24) O=sd_data_serial_host0.data_out_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=data_in_rx_fifo(23) D=sd_data_serial_host0.data_out_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(23) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(23) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=data_in_rx_fifo(22) D=sd_data_serial_host0.data_out_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(22) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(22) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(31) I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(31) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100110011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_serial_host0.data_send_index(4) D=sd_data_serial_host0.data_send_index_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.data_send_index(3) D=sd_data_serial_host0.data_send_index_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.bus_4bit_reg I1=sd_data_serial_host0.data_send_index(3) I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 O=sd_data_serial_host0.data_send_index_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(0) O=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=sd_data_serial_host0.data_send_index(2) D=sd_data_serial_host0.data_send_index_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_send_index(0) I1=sd_data_serial_host0.data_send_index(1) I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 O=sd_data_serial_host0.data_send_index_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.data_send_index(1) D=sd_data_serial_host0.data_send_index_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(0) O=sd_data_serial_host0.data_send_index_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.data_send_index(0) D=sd_data_serial_host0.data_send_index_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.data_send_index_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.data_send_index_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.bus_4bit_reg I1=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.data_send_index_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100100010111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.rd_ff_CQZ_QEN I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 O=sd_data_serial_host0.data_send_index_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_serial_host0.last_din(3) D=sd_data_serial_host0.last_din_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.last_din(2) D=sd_data_serial_host0.last_din_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](14) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](14) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](14) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](14) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(4) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](26) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](26) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](26) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](26) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](30) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](30) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](30) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](30) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](6) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](6) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](6) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](6) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(4) I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](18) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](18) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](18) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](18) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_data_serial_host0.last_din(1) D=sd_data_serial_host0.last_din_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](13) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](13) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](13) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](13) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](29) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](29) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](29) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](29) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](5) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](5) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](5) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](5) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](21) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](21) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](21) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](21) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110000001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](9) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](9) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](9) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](9) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011110001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](1) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](1) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](17) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](17) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](17) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](17) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt ff CQZ=sd_data_serial_host0.last_din(0) D=sd_data_serial_host0.last_din_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(3) I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(4) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(4) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.data_send_index(3) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010111111100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000111110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(4) I3=sd_data_serial_host0.data_send_index(3) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](4) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](4) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](8) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](8) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](8) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](8) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
|
|
.param INIT 0000000000011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](16) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](16) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](16) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](16) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](12) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](12) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](12) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](12) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(3) O=sd_data_serial_host0.last_din_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.bus_4bit_reg I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(1) I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](31) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](31) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](31) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](31) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](15) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](15) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](15) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](15) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](7) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](7) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](7) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](7) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
|
|
.param INIT 0000001100000101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000011101110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](27) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](27) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](27) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](27) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011101111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1010110000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000101000001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1100101000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.bus_4bit_reg I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11001010
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111011110000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101001100000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100000011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10101100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_block I3=sd_data_master0.crc_ok_i O=sd_data_serial_host0.next_block_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_data_serial_host0.next_block D=sd_data_serial_host0.next_block_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.rd_ff_CQZ_QEN I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I3=sd_data_serial_host0.next_block_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.next_block_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(15) I3=sd_data_serial_host0.blkcnt_reg(14) O=sd_data_serial_host0.next_block_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.next_block_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1 I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_I3 O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111111101110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c(4) O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.busy_int I2=sd_data_serial_host0.next_state_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state(3)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100010001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I3 O=sd_data_serial_host0.next_state(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0 I1=sd_data_serial_host0.next_state_LUT4_O_5_I0 I2=sd_data_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_master0.d_read_o I2=sd_data_master0.d_write_o I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111010101010
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I0 I1=sd_data_serial_host0.state(4) I2=sd_data_serial_host0.state(5) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_1_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111010101010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_block_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3 I2=sd_data_serial_host0.state(4) I3=sd_data_serial_host0.state(5) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.state(5) I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3 I3=sd_data_serial_host0.state(4) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.state(0) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.state(1) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.state(1) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I3=sd_data_serial_host0.state(0) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.state(2) I3=sd_data_serial_host0.state(3) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.state(3) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.state(2) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.state(5) I3=sd_data_serial_host0.state(4) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.state(2) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=sd_data_serial_host0.state(3) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.state(0) I3=sd_data_serial_host0.state(1) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_block_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_5_I0 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101110000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I3=sd_data_serial_host0.DAT_dat_reg(0) O=sd_data_serial_host0.next_state(5)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11110100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_5_I0 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2 O=sd_data_serial_host0.next_state_LUT4_O_2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_block_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I3 O=sd_data_serial_host0.next_state(4)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(15) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(9) I1=sd_data_serial_host0.transf_cnt(8) I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(11) I1=sd_data_serial_host0.transf_cnt(10) I2=sd_data_serial_host0.data_cycles(11) I3=sd_data_serial_host0.data_cycles(10) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.transf_cnt(6) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(6) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(1) I1=sd_data_serial_host0.data_cycles(2) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011101111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(14) I1=sd_data_serial_host0.data_cycles(14) I2=sd_data_serial_host0.transf_cnt(15) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(1) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000100110010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.data_cycles(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011010101010011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0 I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011110000000010
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(3) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
|
|
.param INIT 0000000000001110
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000000011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(0) I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.data_cycles(0) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0011000100000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.data_cycles(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(3) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11101000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.transf_cnt(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1 I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.transf_cnt(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.transf_cnt(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.data_cycles(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(0) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001001000000100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(3) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.data_cycles(10) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000010100001100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(12) I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(15) I1=sd_data_serial_host0.transf_cnt(14) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 00001011
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(14) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.transf_cnt(15) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(13) I1=sd_data_serial_host0.transf_cnt(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000111010101111
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(12) I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110111000001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(8) I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110101101111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.transf_cnt(10) I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101001100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(7) I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000110100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.data_cycles(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(5) I1=sd_data_serial_host0.transf_cnt(5) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.transf_cnt(6) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(6) I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011000010111011
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(11) I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.data_cycles(1) I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011111011010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101111010110111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I1 I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 00011110
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I1 I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O_LUT4_I3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.transf_cnt(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100000000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(1) I3=sd_data_serial_host0.data_cycles(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(0) I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1101010011011101
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(2) I2=sd_data_serial_host0.data_cycles(1) I3=sd_data_serial_host0.data_cycles(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I3_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.next_state_LUT4_O_3_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_master0.d_read_o I3=sd_data_master0.d_write_o O=sd_data_serial_host0.next_state_LUT4_O_3_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.next_state_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state(2)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
|
|
.param INIT 0000111110001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(15) I3=sd_data_serial_host0.DAT_dat_reg(0) O=sd_data_serial_host0.next_state_LUT4_O_4_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001110001
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101010011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 0000011100001000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(12) I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100110111010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0101010011111101
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.data_cycles(11) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11010100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(8) I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
|
|
.param INIT 0010101110110010
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.transf_cnt(13) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000011100000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_5_I0 I1=sd_data_serial_host0.next_state_LUT4_O_5_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.next_state_LUT4_O_5_I3 O=sd_data_serial_host0.next_state(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100000011111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_4_I0 O=sd_data_serial_host0.next_state_LUT4_O_5_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_master0.d_read_o I1=sd_data_master0.d_write_o I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_5_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000010111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=sd_data_serial_host0.next_block_LUT4_I2_O I3=sd_data_serial_host0.busy_int O=sd_data_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(0) I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(2) O=sd_data_serial_host0.next_state_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.rd I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(0) O=sd_data_serial_host0.rd_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_data_serial_host0.rd_LUT4_I1_O O=sd_data_serial_host0.rd_LUT4_I1_O_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001011000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I3=sd_data_serial_host0.rd O=sd_data_serial_host0.rd_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt ff CQZ=sd_data_serial_host0.rd D=sd_data_serial_host0.rd_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=sd_data_serial_host0.rd_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_serial_host0.rd_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=sd_data_serial_host0.state(5) D=sd_data_serial_host0.next_state(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.state(4) D=sd_data_serial_host0.next_state(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.state(3) D=sd_data_serial_host0.next_state(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.state(2) D=sd_data_serial_host0.next_state(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.state(1) D=sd_data_serial_host0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.state(0) D=sd_data_serial_host0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_cmd_master0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(15) D=sd_data_serial_host0.transf_cnt_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(14) D=sd_data_serial_host0.transf_cnt_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(5) D=sd_data_serial_host0.transf_cnt_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(4) D=sd_data_serial_host0.transf_cnt_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I1=sd_data_serial_host0.transf_cnt(3) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(3) D=sd_data_serial_host0.transf_cnt_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 O=sd_data_serial_host0.transf_cnt_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(2) D=sd_data_serial_host0.transf_cnt_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(1) D=sd_data_serial_host0.transf_cnt_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.transf_cnt_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(0) D=sd_data_serial_host0.transf_cnt_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.transf_cnt_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3 I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.transf_cnt(14) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(13) D=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(12) D=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(11) D=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(10) D=sd_data_serial_host0.transf_cnt_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(9) D=sd_data_serial_host0.transf_cnt_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.transf_cnt_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(8) D=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(8) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(8) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(7) I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(7) D=sd_data_serial_host0.transf_cnt_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3 I1=sd_data_serial_host0.transf_cnt(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.transf_cnt(6) D=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3 I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.transf_cnt(14) I3=sd_data_serial_host0.transf_cnt(15) O=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_data_serial_host0.we_LUT4_I1_I3 O=sd_data_serial_host0.we_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_data_serial_host0.we_LUT4_I1_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.we_LUT4_I3_I2 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.we_LUT4_I1_I3 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_data_serial_host0.we_LUT4_I3_I2 O=sd_data_serial_host0.we_LUT4_I1_4_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_data_serial_host0.we_LUT4_I3_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_5_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) O=sd_data_serial_host0.we_LUT4_I1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_data_serial_host0.we_LUT4_I3_I2 I3=sd_data_serial_host0.we O=sd_data_serial_host0.we_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_data_serial_host0.we_LUT4_I1_I3 I3=sd_data_serial_host0.we O=sd_data_serial_host0.we_LUT4_I3_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_data_serial_host0.we_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_serial_host0.we D=sd_data_serial_host0.we_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.bus_4bit_reg I1=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.we_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 O=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.we_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01011100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.next_state_LUT4_O_I1 I2=sd_data_xfer_trig0.next_state_LUT4_O_I2 I3=sd_data_xfer_trig0.r_w_i O=sd_data_xfer_trig0.next_state(1)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=cmd_int_status_reg_cross.in(1) I1=sd_data_xfer_trig0.next_state_LUT4_O_1_I1 I2=sd_data_xfer_trig0.next_state_LUT4_O_I2 I3=command_reg_cross.out(6) O=sd_data_xfer_trig0.next_state(0)
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111010001000100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.state(0) I2=sd_data_xfer_trig0.state(1) I3=cmd_int_status_reg_cross.in(0) O=sd_data_xfer_trig0.next_state_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_int_status_reg_cross.in(0) I2=sd_data_xfer_trig0.state(0) I3=sd_data_xfer_trig0.state(1) O=sd_data_xfer_trig0.next_state_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.r_w_reg_ff_CQZ_QEN I2=cmd_start_cross.sync_clk_b(1) I3=cmd_start_cross.sync_clk_b(2) O=sd_data_xfer_trig0.next_state_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=command_reg_cross.out(5) I3=command_reg_cross.out(6) O=sd_data_xfer_trig0.r_w_i
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.r_w_reg I2=sd_data_xfer_trig0.state(1) I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.start_rx_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.state(1) I2=sd_data_xfer_trig0.r_w_reg I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.start_tx_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=sd_data_xfer_trig0.r_w_reg D=sd_data_xfer_trig0.r_w_i QCK=argument_reg_cross.clk_b QEN=sd_data_xfer_trig0.r_w_reg_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:100.1-124.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_xfer_trig0.state(1) I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.r_w_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_data_master0.next_state_LUT4_O_2_I3 I1=sd_data_master0.state(0) I2=sd_data_master0.start_tx_i I3=sd_data_master0.start_rx_i O=sd_data_master0.next_state_LUT4_O_1_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 0000000100000000
|
|
.subckt ff CQZ=sd_data_master0.start_rx_i D=sd_data_xfer_trig0.start_rx_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_xfer_trig0.start_rx_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:100.1-124.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_xfer_trig0.state(1) I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.start_rx_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111
|
|
.subckt ff CQZ=sd_data_master0.start_tx_i D=sd_data_xfer_trig0.start_tx_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_xfer_trig0.start_rx_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:100.1-124.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_data_xfer_trig0.state(1) D=sd_data_xfer_trig0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:90.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_xfer_trig0.state(0) D=sd_data_xfer_trig0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:90.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.wbm_ack_i I3=sd_fifo_filler0.wbm_cyc_o O=sd_fifo_filler0.fifo_rd
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_fifo_filler0.fifo_rd_ack D=sd_fifo_filler0.fifo_rd_ack_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_cmd_master0.rst
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.fifo_rd I3=sd_fifo_filler0.fifo_rd_reg O=sd_fifo_filler0.fifo_rd_ack_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt ff CQZ=sd_fifo_filler0.fifo_rd_reg D=sd_fifo_filler0.fifo_rd QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.empty D=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:279.1-280.68|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111101000000
|
|
.subckt LUT4 I0=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010001000001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110000100011110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(1) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt ff CQZ=sd_data_master0.rx_fifo_full_i D=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:282.1-284.94|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111111100010000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110100101111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011010011111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001011000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110011101111110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:165.1-168.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst_r D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:170.1-172.25|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3 I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=m_wb_dat_o_LUT4_O_7_I3 D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1011
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:174.1-177.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst_r D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:179.1-181.25|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_data_master0.tx_fifo_empty_i D=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:279.1-280.68|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(1) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(4) O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001000000001001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) I3=sd_data_serial_host0.rd_LUT4_I1_O_LUT4_I3_O O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001011000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010001000001
|
|
.subckt LUT4 I0=sd_data_master0.tx_fifo_full_i I1=sd_data_master0.tx_cycle_ff_CQZ_D I2=sd_data_master0.next_state_LUT4_O_1_I3 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_master0.next_state_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
|
|
.param INIT 0000000011111000
|
|
.subckt LUT4 I0=sd_data_master0.state(2) I1=sd_data_master0.tx_fifo_full_i I2=sd_data_master0.state(0) I3=sd_data_master0.state(1) O=sd_data_master0.d_write_o_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001001111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.start_tx_fifo_o I3=sd_data_master0.tx_fifo_full_i O=m_wb_stb_o_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_data_master0.tx_fifo_full_i D=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:282.1-284.94|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0100111101000100
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1001111111110011
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=m_wb_stb_o_LUT4_I3_O I3=sd_data_master0.start_tx_fifo_o O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1111011010011111
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110011101111110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110100110010110
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001010000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0110100110010110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:165.1-168.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
|
|
.param INIT 0000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01101001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
|
|
.param INIT 00000111
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 10010000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
|
|
.param INIT 0001111000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
|
|
.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:174.1-177.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.rst I3=sd_fifo_filler0.offset_ff_CQZ_31_QEN O=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(31) D=sd_fifo_filler0.offset_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(30) D=sd_fifo_filler0.offset_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(21) D=sd_fifo_filler0.offset_ff_CQZ_10_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_10_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_10_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(19) I2=sd_fifo_filler0.offset(20) I3=sd_fifo_filler0.offset(21) O=sd_fifo_filler0.offset_ff_CQZ_10_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(20) D=sd_fifo_filler0.offset_ff_CQZ_11_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(19) I2=sd_fifo_filler0.offset(20) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_11_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(19) D=sd_fifo_filler0.offset_ff_CQZ_12_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(19) I3=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_12_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(16) I2=sd_fifo_filler0.offset(17) I3=sd_fifo_filler0.offset(18) O=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(18) D=sd_fifo_filler0.offset_ff_CQZ_13_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_13_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_13_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(16) I2=sd_fifo_filler0.offset(17) I3=sd_fifo_filler0.offset(18) O=sd_fifo_filler0.offset_ff_CQZ_13_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(17) D=sd_fifo_filler0.offset_ff_CQZ_14_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(16) I2=sd_fifo_filler0.offset(17) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_14_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(16) D=sd_fifo_filler0.offset_ff_CQZ_15_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(16) I3=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_15_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(13) I2=sd_fifo_filler0.offset(14) I3=sd_fifo_filler0.offset(15) O=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(15) D=sd_fifo_filler0.offset_ff_CQZ_16_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_16_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_16_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(13) I2=sd_fifo_filler0.offset(14) I3=sd_fifo_filler0.offset(15) O=sd_fifo_filler0.offset_ff_CQZ_16_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(14) D=sd_fifo_filler0.offset_ff_CQZ_17_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(13) I2=sd_fifo_filler0.offset(14) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_17_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(13) D=sd_fifo_filler0.offset_ff_CQZ_18_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(13) I3=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_18_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(10) I2=sd_fifo_filler0.offset(11) I3=sd_fifo_filler0.offset(12) O=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(12) D=sd_fifo_filler0.offset_ff_CQZ_19_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_19_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_19_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(10) I2=sd_fifo_filler0.offset(11) I3=sd_fifo_filler0.offset(12) O=sd_fifo_filler0.offset_ff_CQZ_19_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(30) I3=sd_fifo_filler0.offset_ff_CQZ_D_LUT4_O_I0 O=sd_fifo_filler0.offset_ff_CQZ_1_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(29) D=sd_fifo_filler0.offset_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(11) D=sd_fifo_filler0.offset_ff_CQZ_20_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(10) I2=sd_fifo_filler0.offset(11) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_20_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(10) D=sd_fifo_filler0.offset_ff_CQZ_21_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(10) I3=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_21_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(9) D=sd_fifo_filler0.offset_ff_CQZ_22_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_22_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_22_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O I1=sd_fifo_filler0.offset(7) I2=sd_fifo_filler0.offset(8) I3=sd_fifo_filler0.offset(9) O=sd_fifo_filler0.offset_ff_CQZ_22_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(8) D=sd_fifo_filler0.offset_ff_CQZ_23_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O I1=sd_fifo_filler0.offset(7) I2=sd_fifo_filler0.offset(8) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_23_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(7) D=sd_fifo_filler0.offset_ff_CQZ_24_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(7) I3=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_24_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(6) D=sd_fifo_filler0.offset_ff_CQZ_25_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(6) I3=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_25_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset(6) I3=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O I1=sd_fifo_filler0.offset(7) I2=sd_fifo_filler0.offset(8) I3=sd_fifo_filler0.offset(9) O=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.offset(5) I2=sd_fifo_filler0.offset(4) I3=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(5) D=sd_fifo_filler0.offset_ff_CQZ_26_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(4) I2=sd_fifo_filler0.offset(5) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_26_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(4) D=sd_fifo_filler0.offset_ff_CQZ_27_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(4) I3=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_27_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset(3) I3=sd_fifo_filler0.offset(2) O=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(3) D=sd_fifo_filler0.offset_ff_CQZ_28_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(3) I3=sd_fifo_filler0.offset(2) O=sd_fifo_filler0.offset_ff_CQZ_28_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(2) D=sd_fifo_filler0.offset_ff_CQZ_29_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset(2) O=sd_fifo_filler0.offset_ff_CQZ_29_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(28) I2=sd_fifo_filler0.offset(29) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_2_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(28) D=sd_fifo_filler0.offset_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(1) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(0) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset_ff_CQZ_31_QEN I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1110
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(28) I3=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_3_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(25) I2=sd_fifo_filler0.offset(26) I3=sd_fifo_filler0.offset(27) O=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(27) D=sd_fifo_filler0.offset_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_4_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_4_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(25) I2=sd_fifo_filler0.offset(26) I3=sd_fifo_filler0.offset(27) O=sd_fifo_filler0.offset_ff_CQZ_4_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(26) D=sd_fifo_filler0.offset_ff_CQZ_5_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(25) I2=sd_fifo_filler0.offset(26) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_5_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(25) D=sd_fifo_filler0.offset_ff_CQZ_6_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(25) I3=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_6_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(22) I2=sd_fifo_filler0.offset(23) I3=sd_fifo_filler0.offset(24) O=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(24) D=sd_fifo_filler0.offset_ff_CQZ_7_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_7_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_7_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(22) I2=sd_fifo_filler0.offset(23) I3=sd_fifo_filler0.offset(24) O=sd_fifo_filler0.offset_ff_CQZ_7_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
|
|
.param INIT 1000000001111111
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(23) D=sd_fifo_filler0.offset_ff_CQZ_8_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(22) I2=sd_fifo_filler0.offset(23) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_8_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt ff CQZ=sd_fifo_filler0.offset(22) D=sd_fifo_filler0.offset_ff_CQZ_9_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(22) I3=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_9_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01100000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(19) I2=sd_fifo_filler0.offset(20) I3=sd_fifo_filler0.offset(21) O=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000000000000000
|
|
.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.offset(30) I2=sd_fifo_filler0.offset(31) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 0111100000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.offset(29) I2=sd_fifo_filler0.offset(28) I3=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_D_LUT4_O_I0
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt ff CQZ=software_reset_reg_cross.sync_clk_b[0] D=sd_controller_wb0.software_reset_reg QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:391.23-391.131|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=software_reset_reg_cross.out D=software_reset_reg_cross.sync_clk_b[0] QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:391.23-391.131|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](15) D=sd_controller_wb0.timeout_reg(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](14) D=sd_controller_wb0.timeout_reg(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](5) D=sd_controller_wb0.timeout_reg(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](4) D=sd_controller_wb0.timeout_reg(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](3) D=sd_controller_wb0.timeout_reg(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](2) D=sd_controller_wb0.timeout_reg(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](1) D=sd_controller_wb0.timeout_reg(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](0) D=sd_controller_wb0.timeout_reg(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](13) D=sd_controller_wb0.timeout_reg(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](12) D=sd_controller_wb0.timeout_reg(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](11) D=sd_controller_wb0.timeout_reg(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](10) D=sd_controller_wb0.timeout_reg(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](9) D=sd_controller_wb0.timeout_reg(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](8) D=sd_controller_wb0.timeout_reg(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](7) D=sd_controller_wb0.timeout_reg(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](6) D=sd_controller_wb0.timeout_reg(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(15) D=timeout_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(14) D=timeout_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(5) D=timeout_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(4) D=timeout_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(3) D=timeout_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(2) D=timeout_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(1) D=timeout_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(0) D=timeout_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(13) D=timeout_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(12) D=timeout_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(11) D=timeout_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(10) D=timeout_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(9) D=timeout_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(8) D=timeout_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(7) D=timeout_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt ff CQZ=sd_cmd_master0.timeout_i(6) D=timeout_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_cyc_i I2=sd_controller_wb0.wb_stb_i I3=sd_controller_wb0.wb_ack_o O=sd_controller_wb0.wb_ack_o_ff_CQZ_D
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_cyc_i I2=sd_controller_wb0.wb_stb_i I3=wb_cyc_i_LUT4_I1_1_I3 O=wb_cyc_i_LUT4_I1_1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 01000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 O=wb_cyc_i_LUT4_I1_1_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
|
|
.param INIT 01110000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(3) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(1) I3=sd_controller_wb0.wb_adr_i(0) O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 0001
|
|
.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(2) I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=wb_we_i_LUT4_I2_O O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
|
|
.param EQN "(~I0*I1*I2*I3)"
|
|
.param INIT 0100000000000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 10000000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(1) I2=sd_controller_wb0.wb_adr_i(0) I3=sd_controller_wb0.wb_adr_i(3) O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*~I2*I3)"
|
|
.param INIT 00000001
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(4) I3=sd_controller_wb0.wb_adr_i(5) O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(~I0*~I1*I2*I3)"
|
|
.param INIT 00010000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_ack_o I2=sd_controller_wb0.wb_stb_i I3=sd_controller_wb0.wb_cyc_i O=wb_we_i_LUT4_I2_I3
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
|
|
.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
|
|
.param INIT 11111000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_we_i I3=wb_we_i_LUT4_I2_I3 O=wb_we_i_LUT4_I2_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.command_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.timeout_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.block_size_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.block_count_reg_ff_CQZ_QEN
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=wb_we_i_LUT4_I2_O_LUT4_I2_5_O
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
|
|
.param EQN "(I0*I1*I2*I3)"
|
|
.param INIT 1000
|
|
.end
|