mirror of https://github.com/lnis-uofu/SOFA.git
196 lines
8.5 KiB
Verilog
196 lines
8.5 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// sd_controller_wb.v ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// Description ////
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//// Wishbone interface responsible for comunication with core ////
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//// ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// Based on original work by ////
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//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
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//// ////
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//// Copyright (C) 2009 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "sd_defines.h"
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module sd_controller_wb(
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// WISHBONE slave
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
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cmd_start,
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data_int_rst,
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cmd_int_rst,
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argument_reg,
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command_reg,
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response_0_reg,
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response_1_reg,
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response_2_reg,
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response_3_reg,
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software_reset_reg,
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timeout_reg,
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block_size_reg,
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controll_setting_reg,
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cmd_int_status_reg,
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cmd_int_enable_reg,
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clock_divider_reg,
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block_count_reg,
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dma_addr_reg,
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data_int_status_reg,
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data_int_enable_reg
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);
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// WISHBONE common
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input wb_clk_i; // WISHBONE clock
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input wb_rst_i; // WISHBONE reset
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input [31:0] wb_dat_i; // WISHBONE data input
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output reg [31:0] wb_dat_o; // WISHBONE data output
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// WISHBONE error output
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// WISHBONE slave
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input [7:0] wb_adr_i; // WISHBONE address input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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output reg wb_ack_o; // WISHBONE acknowledge output
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output reg cmd_start;
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//Buss accessible registers
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output reg [31:0] argument_reg;
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output reg [`CMD_REG_SIZE-1:0] command_reg;
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input wire [31:0] response_0_reg;
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input wire [31:0] response_1_reg;
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input wire [31:0] response_2_reg;
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input wire [31:0] response_3_reg;
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output reg [0:0] software_reset_reg;
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output reg [15:0] timeout_reg;
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output reg [`BLKSIZE_W-1:0] block_size_reg;
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output reg [15:0] controll_setting_reg;
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input wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
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output reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
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output reg [7:0] clock_divider_reg;
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input wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
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output reg [`INT_DATA_SIZE-1:0] data_int_enable_reg;
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//Register Controll
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output reg data_int_rst;
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output reg cmd_int_rst;
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output reg [`BLKCNT_W-1:0]block_count_reg;
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output reg [31:0] dma_addr_reg;
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parameter voltage_controll_reg = `SUPPLY_VOLTAGE_mV;
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parameter capabilies_reg = 16'b0000_0000_0000_0000;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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begin
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if (wb_rst_i)begin
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argument_reg <= 0;
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command_reg <= 0;
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software_reset_reg <= 0;
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timeout_reg <= 0;
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block_size_reg <= `RESET_BLOCK_SIZE;
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controll_setting_reg <= 0;
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cmd_int_enable_reg <= 0;
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clock_divider_reg <= `RESET_CLK_DIV;
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wb_ack_o <= 0;
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cmd_start <= 0;
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data_int_rst <= 0;
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data_int_enable_reg <= 0;
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cmd_int_rst <= 0;
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block_count_reg <= 0;
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dma_addr_reg <= 0;
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end
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else
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begin
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cmd_start <= 1'b0;
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data_int_rst <= 0;
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cmd_int_rst <= 0;
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if ((wb_stb_i & wb_cyc_i) || wb_ack_o)begin
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if (wb_we_i) begin
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case (wb_adr_i)
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`argument: begin
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argument_reg <= wb_dat_i;
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cmd_start <= 1'b1;
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end
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`command: command_reg <= wb_dat_i[`CMD_REG_SIZE-1:0];
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`reset: software_reset_reg <= wb_dat_i[0];
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`timeout: timeout_reg <= wb_dat_i[15:0];
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`blksize: block_size_reg <= wb_dat_i[`BLKSIZE_W-1:0];
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`controller: controll_setting_reg <= wb_dat_i[15:0];
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`cmd_iser: cmd_int_enable_reg <= wb_dat_i[4:0];
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`cmd_isr: cmd_int_rst <= 1;
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`clock_d: clock_divider_reg <= wb_dat_i[7:0];
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`data_isr: data_int_rst <= 1;
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`data_iser: data_int_enable_reg <= wb_dat_i[`INT_DATA_SIZE-1:0];
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`dst_src_addr: dma_addr_reg <= wb_dat_i;
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`blkcnt: block_count_reg <= wb_dat_i[`BLKCNT_W-1:0];
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endcase
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end
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wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
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end
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end
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end
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always @(posedge wb_clk_i or posedge wb_rst_i)begin
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if (wb_rst_i == 1)
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wb_dat_o <= 0;
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else
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if (wb_stb_i & wb_cyc_i) begin //CS
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case (wb_adr_i)
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`argument: wb_dat_o <= argument_reg;
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`command: wb_dat_o <= command_reg;
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`resp0: wb_dat_o <= response_0_reg;
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`resp1: wb_dat_o <= response_1_reg;
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`resp2: wb_dat_o <= response_2_reg;
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`resp3: wb_dat_o <= response_3_reg;
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`controller: wb_dat_o <= controll_setting_reg;
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`blksize: wb_dat_o <= block_size_reg;
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`voltage: wb_dat_o <= voltage_controll_reg;
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`reset: wb_dat_o <= software_reset_reg;
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`timeout: wb_dat_o <= timeout_reg;
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`cmd_isr: wb_dat_o <= cmd_int_status_reg;
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`cmd_iser: wb_dat_o <= cmd_int_enable_reg;
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`clock_d: wb_dat_o <= clock_divider_reg;
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`capa: wb_dat_o <= capabilies_reg;
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`data_isr: wb_dat_o <= data_int_status_reg;
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`blkcnt: wb_dat_o <= block_count_reg;
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`data_iser: wb_dat_o <= data_int_enable_reg;
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`dst_src_addr: wb_dat_o <= dma_addr_reg;
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endcase
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end
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end
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endmodule
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