mirror of https://github.com/lnis-uofu/SOFA.git
80 lines
3.8 KiB
Verilog
80 lines
3.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE SD Card Controller IP Core ////
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//// ////
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//// sd_clock_divider.v ////
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//// ////
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//// This file is part of the WISHBONE SD Card ////
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//// Controller IP Core project ////
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//// http://opencores.org/project,sd_card_controller ////
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//// ////
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//// Description ////
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//// Control of sd card clock rate ////
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//// ////
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//// Author(s): ////
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//// - Marek Czerski, ma.czerski@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// Based on original work by ////
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//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
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//// ////
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//// Copyright (C) 2009 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module sd_clock_divider (
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input CLK,
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input [7:0] DIVIDER,
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input RST,
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output SD_CLK
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);
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reg [7:0] ClockDiv;
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reg SD_CLK_O;
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//assign SD_CLK = DIVIDER[7] ? CLK : SD_CLK_O;
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assign SD_CLK = SD_CLK_O;
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always @(posedge CLK or posedge RST)
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begin
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if (RST) begin
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ClockDiv <= 8'b0000_0000;
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SD_CLK_O <= 0;
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end
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else if (ClockDiv == DIVIDER) begin
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ClockDiv <= 0;
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SD_CLK_O <= ~SD_CLK_O;
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end else begin
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ClockDiv <= ClockDiv + 8'h1;
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SD_CLK_O <= SD_CLK_O;
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end
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end
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endmodule
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