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SOFA/FPGA22_HIER_SKY_PNR/modules/verilog
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Ganesh Gore 72ff141046 [DESIGN] Updated FPGA22 Design 
+ Utilization increased to 60%
+ Added track offset
+ Added Power ring
+ Added Tapcells
+ Added additional reports and screenshot to track improvements
 		2020-10-27 14:54:19 -06:00
..
cbx_1__0__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__0__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__0__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__1__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__1__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__1__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__2__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__2__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cbx_1__2__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cby_0__1__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cby_0__1__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cby_0__1__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cby_1__1__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cby_1__1__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
cby_1__1__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__0__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__0__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__0__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__1__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__1__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__1__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__2__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__2__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_0__2__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__0__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__0__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__0__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__1__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__1__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__1__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__2__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__2__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_1__2__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__0__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__0__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__0__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__1__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__1__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__1__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__2__icv_in_design.fm.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__2__icv_in_design.lvs.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
sb_2__2__icv_in_design.pt.v [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00