mirror of https://github.com/lnis-uofu/SOFA.git
37 lines
1.5 KiB
ReStructuredText
37 lines
1.5 KiB
ReStructuredText
Device Overview
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All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
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All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
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The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
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We aims to empower embedded applications with its low-cost design approach but high-density architecture.
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- Native support on shift registers
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- Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
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.. table:: Logic capacity of High Density (HD) FPGA IP
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+--------------------------+------------+
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| Resource Type | Capacity |
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+==========================+============+
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| Look-Up Tables [1]_ | 1152 |
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+--------------------------+------------+
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| Flip-flops | 2204 |
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+--------------------------+------------+
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| Max. Configuration Speed | TBD |
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+--------------------------+------------+
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| Max. Operating Speed | TBD |
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+--------------------------+------------+
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| User I/O Pins | 30 |
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+--------------------------+------------+
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| Max. I/O Speed | TBD |
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+--------------------------+------------+
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| Core Voltage | 1.8V |
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+--------------------------+------------+
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.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
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