mirror of https://github.com/lnis-uofu/SOFA.git
108 lines
4.5 KiB
ReStructuredText
108 lines
4.5 KiB
ReStructuredText
.. _io_resource:
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I/O Resources
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-------------
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.. _io_resource_overview:
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Overview
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~~~~~~~~
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The *High-Density* (HD) FPGA IP has 144 I/O pins as shown in :numref:`fig_fpga_io_switch`.
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Among the 144 I/Os,
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- **29 external I/Os** are accessible through the Caravel SoC's *General-Purpose I/Os* (GPIOs).
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- **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details.
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.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components.
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.. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.
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.. warning:: The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in :numref:`fig_fpga_io_switch`.
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.. _fig_fpga_io_switch:
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.. figure:: ./figures/fpga_io_switch.svg
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:scale: 20%
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:alt: I/O arrangement of FPGA IP
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I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
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.. _io_resource_accelerator:
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Accelerator Mode
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~~~~~~~~~~~~~~~~
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When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
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:numref:`fig_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
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.. note:: Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:30] are not connected.
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.. warning:: The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.
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.. _fig_fpga_io_map_wishbone_mode:
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.. figure:: ./figures/fpga_io_map_wishbone_mode.svg
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:scale: 20%
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:alt: I/O arrangement of FPGA IP when interfacing wishbone bus
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I/O arrangement of *High-Density* (HD) FPGA IP when interfacing wishbone bus
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.. _io_resource_debug:
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Debug Mode
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~~~~~~~~~~
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When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
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:numref:`fig_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.
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.. note:: The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.
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.. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows:
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- all the I/O directionality is set to **input mode**.
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- all the output ports is pulled down to **logic ``0``**.
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.. _fig_fpga_io_map_logic_analyzer_mode:
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.. figure:: ./figures/fpga_io_map_logic_analyzer_mode.svg
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:scale: 20%
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:alt: I/O arrangement of FPGA IP when interfacing logic analyzer
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I/O arrangement of *High-Density* (HD) FPGA IP when interfacing logic analyzer
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.. _io_resource_circuit:
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FPGA I/O Circuit
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~~~~~~~~~~~~~~~~
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As shown in :numref:`fig_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_fpga_arch`) is an digital I/O cell with
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- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
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.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
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- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
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- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
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- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
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- An internal configurable memory element to control the direction of I/O cell
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The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
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- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
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- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
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.. _fig_embedded_io_schematic:
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.. figure:: ./figures/embedded_io_schematic.svg
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:scale: 30%
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:alt: Schematic of embedded I/O cell used in FPGA
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Schematic of embedded I/O cell used in FPGA
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