tangxifan abe56ce2c2 [Script] Rename openfpga task directory to avoid name conflicts in OpenFPGA task directory		2020-10-10 11:06:28 -06:00
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openfpga_shell_script	[Script] Now use variables to redirect the output directory of Verilog/SDC files	2020-10-09 16:00:41 -06:00
skywater_openfpga_task/k4_cc_fdms_2x2/generate_fabric/config	[Script] Rename openfpga task directory to avoid name conflicts in OpenFPGA task directory	2020-10-10 11:06:28 -06:00
repo_setup.py	[Script] Rename openfpga task directory to avoid name conflicts in OpenFPGA task directory	2020-10-10 11:06:28 -06:00