mirror of https://github.com/lnis-uofu/SOFA.git
124 lines
4.3 KiB
Verilog
124 lines
4.3 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Discrete Cosine Transform, MAC unit ////
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//// ////
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//// Virtex-II: Block-Multiplier is used ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: dct_mac.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
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//
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// $Date: 2002-10-31 12:50:03 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/23 09:06:59 rherveille
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// Improved many files.
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// Fixed some bugs in Run-Length-Encoder.
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// Removed dependency on ud_cnt and ro_cnt.
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// Started (Motion)JPEG hardware encoder project.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module dct_mac(clk, ena, dclr, din, coef, result);
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//
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// parameters
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//
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parameter dwidth = 8;
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parameter cwidth = 16;
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parameter mwidth = dwidth + cwidth; // multiplier result
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parameter rwidth = mwidth +3; // add 3 bits for growth
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//
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// inputs & outputs
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//
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input clk; // clock input
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input ena; // clock enable
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input dclr; // start new mac (delayed 1 cycle)
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input [dwidth-1:0] din; // data input
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input [cwidth-1:0] coef; // coefficient input
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output [rwidth-1:0] result; // mac-result
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reg [rwidth -1:0] result;
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//
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// variables
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//
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wire [mwidth-1:0] idin;
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wire [mwidth-1:0] icoef;
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reg [mwidth -1:0] mult_res /* synthesis syn_multstyle="block_mult" syn_pipeline=1*/ ;
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wire [rwidth -1:0] ext_mult_res;
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//
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// module body
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//
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assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
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assign idin = { {(mwidth-dwidth){din[dwidth-1]}}, din};
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// generate multiplier structure
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always @(posedge clk)
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if(ena)
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mult_res <= #1 icoef * idin;
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assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};
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// generate adder structure
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always @(posedge clk)
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if(ena)
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if(dclr)
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result <= #1 ext_mult_res;
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else
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result <= #1 ext_mult_res + result;
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endmodule
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