mirror of https://github.com/lnis-uofu/SOFA.git
120 lines
3.1 KiB
Verilog
120 lines
3.1 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Look-Up Tables
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for frac_lut4 -----
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module frac_lut4(in,
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sram,
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sram_inv,
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mode,
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mode_inv,
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lut2_out,
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lut3_out,
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lut4_out);
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//----- INPUT PORTS -----
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input [0:3] in;
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//----- INPUT PORTS -----
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input [0:15] sram;
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//----- INPUT PORTS -----
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input [0:15] sram_inv;
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//----- INPUT PORTS -----
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input [0:0] mode;
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//----- INPUT PORTS -----
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input [0:0] mode_inv;
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//----- OUTPUT PORTS -----
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output [0:1] lut2_out;
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//----- OUTPUT PORTS -----
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output [0:1] lut3_out;
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//----- OUTPUT PORTS -----
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output [0:0] lut4_out;
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//----- BEGIN wire-connection ports -----
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wire [0:3] in;
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wire [0:1] lut2_out;
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wire [0:1] lut3_out;
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wire [0:0] lut4_out;
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
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wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
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wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
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wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
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wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
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wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
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wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
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.A(mode),
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.B(in[3]),
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.X(sky130_fd_sc_hd__or2_1_0_X));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
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.A(in[0]),
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.Y(sky130_fd_sc_hd__inv_1_0_Y));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
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.A(in[1]),
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.Y(sky130_fd_sc_hd__inv_1_1_Y));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
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.A(in[2]),
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.Y(sky130_fd_sc_hd__inv_1_2_Y));
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sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
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.A(sky130_fd_sc_hd__or2_1_0_X),
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.Y(sky130_fd_sc_hd__inv_1_3_Y));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
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.A(in[0]),
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.X(sky130_fd_sc_hd__buf_2_0_X));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
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.A(in[1]),
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.X(sky130_fd_sc_hd__buf_2_1_X));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
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.A(in[2]),
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.X(sky130_fd_sc_hd__buf_2_2_X));
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sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
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.A(sky130_fd_sc_hd__or2_1_0_X),
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.X(sky130_fd_sc_hd__buf_2_3_X));
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frac_lut4_mux frac_lut4_mux_0_ (
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.in(sram[0:15]),
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.sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}),
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.sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}),
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.lut2_out(lut2_out[0:1]),
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.lut3_out(lut3_out[0:1]),
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.lut4_out(lut4_out));
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endmodule
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// ----- END Verilog module for frac_lut4 -----
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//----- Default net type -----
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`default_nettype none
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