mirror of https://github.com/lnis-uofu/SOFA.git
11 lines
328 B
Verilog
11 lines
328 B
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Decoders for fabric configuration protocol
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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