mirror of https://github.com/lnis-uofu/SOFA.git
581 lines
45 KiB
Verilog
581 lines
45 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Top-level Verilog module for FPGA
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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// ----- Verilog module for fpga_top -----
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module fpga_top(clk,
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Reset,
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IO_ISOL_N,
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pReset,
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prog_clk,
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Test_en,
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gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
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gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
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gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
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ccff_head,
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ccff_tail);
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//----- GLOBAL PORTS -----
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input [0:0] clk;
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//----- GLOBAL PORTS -----
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input [0:0] Reset;
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//----- GLOBAL PORTS -----
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input [0:0] IO_ISOL_N;
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//----- GLOBAL PORTS -----
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input [0:0] pReset;
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//----- GLOBAL PORTS -----
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input [0:0] prog_clk;
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//----- GLOBAL PORTS -----
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input [0:0] Test_en;
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//----- GPIN PORTS -----
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input [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
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//----- GPOUT PORTS -----
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output [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
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//----- GPOUT PORTS -----
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output [0:25] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
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//----- INPUT PORTS -----
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input [0:0] ccff_head;
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//----- OUTPUT PORTS -----
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output [0:0] ccff_tail;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_;
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wire [0:0] cbx_1__0__0_ccff_tail;
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wire [0:10] cbx_1__0__0_chanx_left_out;
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wire [0:10] cbx_1__0__0_chanx_right_out;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
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wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
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wire [0:0] cbx_1__1__0_ccff_tail;
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wire [0:10] cbx_1__1__0_chanx_left_out;
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wire [0:10] cbx_1__1__0_chanx_right_out;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
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wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
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wire [0:0] cby_0__1__0_ccff_tail;
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wire [0:10] cby_0__1__0_chany_bottom_out;
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wire [0:10] cby_0__1__0_chany_top_out;
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wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
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wire [0:0] cby_1__1__0_ccff_tail;
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wire [0:10] cby_1__1__0_chany_bottom_out;
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wire [0:10] cby_1__1__0_chany_top_out;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
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wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
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wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_;
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wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_;
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wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_;
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wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_;
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wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
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wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
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wire [0:0] grid_clb_1__1__undriven_right_width_0_height_0_subtile_0__pin_O_15_;
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wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_cin_0_;
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wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_;
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wire [0:0] grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_;
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wire [0:0] grid_io_bottom_bottom_0_ccff_tail;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_;
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wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_;
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wire [0:0] grid_io_left_left_0_ccff_tail;
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wire [0:0] grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_ccff_tail;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_;
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wire [0:0] grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
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wire [0:0] grid_io_top_top_0_ccff_tail;
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wire [0:0] sb_0__0__0_ccff_tail;
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wire [0:10] sb_0__0__0_chanx_right_out;
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wire [0:10] sb_0__0__0_chany_top_out;
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wire [0:0] sb_0__1__0_ccff_tail;
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wire [0:10] sb_0__1__0_chanx_right_out;
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wire [0:10] sb_0__1__0_chany_bottom_out;
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wire [0:0] sb_1__0__0_ccff_tail;
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wire [0:10] sb_1__0__0_chanx_left_out;
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wire [0:10] sb_1__0__0_chany_top_out;
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wire [0:0] sb_1__1__0_ccff_tail;
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wire [0:10] sb_1__1__0_chanx_left_out;
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wire [0:10] sb_1__1__0_chany_bottom_out;
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// ----- BEGIN Local short connections -----
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// ----- END Local short connections -----
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// ----- BEGIN Local output short connections -----
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// ----- END Local output short connections -----
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grid_io_top_top grid_io_top_top_1__2_ (
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.IO_ISOL_N(IO_ISOL_N),
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.pReset(pReset),
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.prog_clk(prog_clk),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:7]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:7]),
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.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:7]),
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.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
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.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
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.ccff_head(cbx_1__1__0_ccff_tail),
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.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
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.bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
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|
.ccff_tail(grid_io_top_top_0_ccff_tail));
|
|
|
|
grid_io_right_right grid_io_right_right_2__1_ (
|
|
.IO_ISOL_N(IO_ISOL_N),
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:15]),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:15]),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:15]),
|
|
.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
|
|
.left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
|
|
.ccff_head(grid_io_bottom_bottom_0_ccff_tail),
|
|
.left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.ccff_tail(grid_io_right_right_0_ccff_tail));
|
|
|
|
grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ (
|
|
.IO_ISOL_N(IO_ISOL_N),
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:24]),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:24]),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:24]),
|
|
.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
|
|
.top_width_0_height_0_subtile_8__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_),
|
|
.ccff_head(ccff_head),
|
|
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_),
|
|
.ccff_tail(grid_io_bottom_bottom_0_ccff_tail));
|
|
|
|
grid_io_left_left grid_io_left_left_0__1_ (
|
|
.IO_ISOL_N(IO_ISOL_N),
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25]),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25]),
|
|
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25]),
|
|
.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
|
|
.ccff_head(cby_0__1__0_ccff_tail),
|
|
.right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.ccff_tail(grid_io_left_left_0_ccff_tail));
|
|
|
|
grid_clb grid_clb_1__1_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.Test_en(Test_en),
|
|
.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
|
|
.top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
|
|
.top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
|
|
.top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
|
|
.top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_),
|
|
.top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__1__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
|
|
.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
|
|
.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
|
|
.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
|
|
.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
|
|
.ccff_head(cby_1__1__0_ccff_tail),
|
|
.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
|
|
.top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
|
|
.top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
|
|
.top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_),
|
|
.top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_),
|
|
.top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_),
|
|
.top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_),
|
|
.top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_),
|
|
.right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
|
|
.right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_),
|
|
.right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_),
|
|
.right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_),
|
|
.right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_),
|
|
.right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_),
|
|
.right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_),
|
|
.right_width_0_height_0_subtile_0__pin_O_15_(grid_clb_1__1__undriven_right_width_0_height_0_subtile_0__pin_O_15_),
|
|
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
|
|
.bottom_width_0_height_0_subtile_0__pin_sc_out_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
|
|
.bottom_width_0_height_0_subtile_0__pin_cout_0_(grid_clb_1__1__undriven_bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
|
.ccff_tail(ccff_tail));
|
|
|
|
sb_0__0_ sb_0__0_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.chany_top_in(cby_0__1__0_chany_bottom_out[0:10]),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.chanx_right_in(cbx_1__0__0_chanx_left_out[0:10]),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_),
|
|
.ccff_head(sb_0__1__0_ccff_tail),
|
|
.chany_top_out(sb_0__0__0_chany_top_out[0:10]),
|
|
.chanx_right_out(sb_0__0__0_chanx_right_out[0:10]),
|
|
.ccff_tail(sb_0__0__0_ccff_tail));
|
|
|
|
sb_0__1_ sb_0__1_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.chanx_right_in(cbx_1__1__0_chanx_left_out[0:10]),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_),
|
|
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_),
|
|
.chany_bottom_in(cby_0__1__0_chany_top_out[0:10]),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.ccff_head(grid_io_top_top_0_ccff_tail),
|
|
.chanx_right_out(sb_0__1__0_chanx_right_out[0:10]),
|
|
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:10]),
|
|
.ccff_tail(sb_0__1__0_ccff_tail));
|
|
|
|
sb_1__0_ sb_1__0_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.chany_top_in(cby_1__1__0_chany_bottom_out[0:10]),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_),
|
|
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_),
|
|
.top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.chanx_left_in(cbx_1__0__0_chanx_right_out[0:10]),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_8__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_8__pin_inpad_0_),
|
|
.ccff_head(grid_io_left_left_0_ccff_tail),
|
|
.chany_top_out(sb_1__0__0_chany_top_out[0:10]),
|
|
.chanx_left_out(sb_1__0__0_chanx_left_out[0:10]),
|
|
.ccff_tail(sb_1__0__0_ccff_tail));
|
|
|
|
sb_1__1_ sb_1__1_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.chany_bottom_in(cby_1__1__0_chany_top_out[0:10]),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_9_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_11_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_12_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_13_),
|
|
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_14_),
|
|
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:10]),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
|
|
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_3_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_4_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_5_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_6_),
|
|
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_7_),
|
|
.ccff_head(grid_io_right_right_0_ccff_tail),
|
|
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:10]),
|
|
.chanx_left_out(sb_1__1__0_chanx_left_out[0:10]),
|
|
.ccff_tail(sb_1__1__0_ccff_tail));
|
|
|
|
cbx_1__0_ cbx_1__0_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.chanx_left_in(sb_0__0__0_chanx_right_out[0:10]),
|
|
.chanx_right_in(sb_1__0__0_chanx_left_out[0:10]),
|
|
.ccff_head(sb_1__0__0_ccff_tail),
|
|
.chanx_left_out(cbx_1__0__0_chanx_left_out[0:10]),
|
|
.chanx_right_out(cbx_1__0__0_chanx_right_out[0:10]),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_8__pin_outpad_0_),
|
|
.ccff_tail(cbx_1__0__0_ccff_tail));
|
|
|
|
cbx_1__1_ cbx_1__1_ (
|
|
.pReset(pReset),
|
|
.prog_clk(prog_clk),
|
|
.chanx_left_in(sb_0__1__0_chanx_right_out[0:10]),
|
|
.chanx_right_in(sb_1__1__0_chanx_left_out[0:10]),
|
|
.ccff_head(sb_1__1__0_ccff_tail),
|
|
.chanx_left_out(cbx_1__1__0_chanx_left_out[0:10]),
|
|
.chanx_right_out(cbx_1__1__0_chanx_right_out[0:10]),
|
|
.top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
|
|
.top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
|
|
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
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.bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
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.bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
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.bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
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.ccff_tail(cbx_1__1__0_ccff_tail));
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cby_0__1_ cby_0__1_ (
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.pReset(pReset),
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.prog_clk(prog_clk),
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.chany_bottom_in(sb_0__0__0_chany_top_out[0:10]),
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.chany_top_in(sb_0__1__0_chany_bottom_out[0:10]),
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.ccff_head(sb_0__0__0_ccff_tail),
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.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:10]),
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.chany_top_out(cby_0__1__0_chany_top_out[0:10]),
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.left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
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.ccff_tail(cby_0__1__0_ccff_tail));
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cby_1__1_ cby_1__1_ (
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.pReset(pReset),
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.prog_clk(prog_clk),
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.chany_bottom_in(sb_1__0__0_chany_top_out[0:10]),
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.chany_top_in(sb_1__1__0_chany_bottom_out[0:10]),
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.ccff_head(cbx_1__0__0_ccff_tail),
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.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:10]),
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.chany_top_out(cby_1__1__0_chany_top_out[0:10]),
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.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
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.right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
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|
.left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
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|
.left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
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|
.left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
|
|
.left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
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|
.left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
|
|
.left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
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.left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
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.ccff_tail(cby_1__1__0_ccff_tail));
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endmodule
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// ----- END Verilog module for fpga_top -----
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//----- Default net type -----
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`default_nettype none
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