mirror of https://github.com/lnis-uofu/SOFA.git
65 lines
3.8 KiB
Verilog
65 lines
3.8 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Fabric Netlist Summary
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// Author: Xifan TANG
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// Organization: University of Utah
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// Date: Sun Feb 19 10:53:27 2023
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ------ Include defines: preproc flags -----
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`include "./SRC/fpga_defines.v"
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// ------ Include user-defined netlists -----
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
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`include "/research/ece/lnis/Share/OpenFPGA_VTR/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
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// ------ Include primitive module netlists -----
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`include "./SRC/sub_module/inv_buf_passgate.v"
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`include "./SRC/sub_module/arch_encoder.v"
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`include "./SRC/sub_module/local_encoder.v"
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`include "./SRC/sub_module/mux_primitives.v"
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`include "./SRC/sub_module/muxes.v"
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`include "./SRC/sub_module/luts.v"
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`include "./SRC/sub_module/wires.v"
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`include "./SRC/sub_module/memories.v"
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`include "./SRC/sub_module/shift_register_banks.v"
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// ------ Include logic block netlists -----
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`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v"
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`include "./SRC/lb/logical_tile_io_mode_io_.v"
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`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
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`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v"
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`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
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`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
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`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
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`include "./SRC/lb/logical_tile_clb_mode_default__fle.v"
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`include "./SRC/lb/logical_tile_clb_mode_clb_.v"
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`include "./SRC/lb/grid_io_top_top.v"
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`include "./SRC/lb/grid_io_right_right.v"
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`include "./SRC/lb/grid_io_bottom_bottom.v"
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`include "./SRC/lb/grid_io_left_left.v"
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`include "./SRC/lb/grid_clb.v"
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// ------ Include routing module netlists -----
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`include "./SRC/routing/sb_0__0_.v"
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`include "./SRC/routing/sb_0__1_.v"
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`include "./SRC/routing/sb_1__0_.v"
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`include "./SRC/routing/sb_1__1_.v"
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`include "./SRC/routing/cbx_1__0_.v"
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`include "./SRC/routing/cbx_1__1_.v"
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`include "./SRC/routing/cby_0__1_.v"
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`include "./SRC/routing/cby_1__1_.v"
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// ------ Include fabric top-level netlists -----
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`include "./SRC/fpga_top.v"
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