mirror of https://github.com/lnis-uofu/SOFA.git
137 lines
7.5 KiB
Tcl
137 lines
7.5 KiB
Tcl
#####################################################################
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# A template script to report timing for A CLB from post-PnR results
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# using Synopsys PrimeTime
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#####################################################################
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##################################
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# Define environment variables
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#
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#set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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if {"SOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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}
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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# Enable preprocessing in Verilog parser
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set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths tr
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm ${SKYWATER_PDK_HOME}/../../LIB"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib"
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} else {
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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}
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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##################################
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# Ensure a clean start
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remove_design -all
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remove_lib -all
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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if {"SOFA_CHD" == ${DEVICE_NAME}} {
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read_lib "${SKYWATER_PDK_HOME}/../../LIB/sky130_uuopenfpga_cc_hd__tt_025C_1v80.lib"
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}
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##################################
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# Read post-PnR netlists
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read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
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# Top-level module name
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set DESIGN_NAME "grid_clb";
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link_design ${DESIGN_NAME}
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#########################################
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# Setup constraints to break combinational loops
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if {${DEVICE_NAME} == "SOFA_HD"} {
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set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
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} else {
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# QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
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# Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
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set_disable_timing */*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
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set_disable_timing */*/*/*/*/*mem*/sky*_fd_sc_hd__dfrtp_*_*_/Q
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#Disable cin/cout paths
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set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cin
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set_disable_timing logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/frac_logic_cout
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}
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#
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##########################################
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## Setup constraints for clocks
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##########################################
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## Setup constraints for paths
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##################################
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# Read post-PnR parasitics
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read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
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##################################
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# Report timing of Connect block
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# LUT4 output timing
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set LUT_INPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/in"
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set LUT4_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut4_out"
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# Walk through all the input pin and output pin paths
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for {set ipin 0} {$ipin < 4} {incr ipin} {
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if {0 == $ipin} {
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report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
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} else {
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report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT4_OUTPUT_PORT_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut4_timing.rpt
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}
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}
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# LUT3 output timing
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set LUT3_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_*/frac_lut4_*_/lut3_out"
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# Walk through all the input pin and output pin paths
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for {set ipin 0} {$ipin < 3} {incr ipin} {
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for {set opin 0} {$opin < 2} {incr opin} {
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if {0 == $ipin && 0 == $opin} {
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report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
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} else {
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report_timing -from ${LUT_INPUT_PORT_NAME}[$ipin] -to ${LUT3_OUTPUT_PORT_NAME}[$opin] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut3_timing.rpt
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}
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}
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}
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# Output selector timing
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set FRAC_LOGIC_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0]"
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set FF_PATH "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff"
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set FLE_OUTPUT_PORT_NAME "logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/fabric_out"
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report_timing -from ${FF_PATH}_0/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
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report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[0] -to ${FLE_OUTPUT_PORT_NAME}[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
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report_timing -from ${FF_PATH}_1/ff_Q[0] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
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report_timing -from ${FRAC_LOGIC_OUTPUT_PORT_NAME}[1] -to ${FLE_OUTPUT_PORT_NAME}[1] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_output_mux_timing.rpt
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# LUT output to FF input timing
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report_timing -from ${LUT4_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
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report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_0/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
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report_timing -from ${LUT3_OUTPUT_PORT_NAME} -to ${FF_PATH}_1/ff_D[0] >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_lut2ff_timing.rpt
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# TODO: Carry logic timing
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##################################
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# Finish and quit
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# Comment it out if you want to debug
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exit
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