mirror of https://github.com/lnis-uofu/SOFA.git
45 lines
1.0 KiB
Verilog
45 lines
1.0 KiB
Verilog
`timescale 1ns/1ps
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module GPIO (A, IE, OE, Y, in, out, mem_out);
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output A;
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output IE;
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output OE;
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output Y;
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input in;
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output out;
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input mem_out;
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assign A = in;
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assign out = Y;
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assign IE = mem_out;
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sky130_fd_sc_hd__inv_1 ie_oe_inv (
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.A (mem_out),
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.Y (OE) );
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endmodule
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//-----------------------------------------------------
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// Function : A minimum input pad
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//-----------------------------------------------------
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module GPIN (
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inout A, // External PAD signal
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output Y // Data input
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);
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// Assume a 4x buf is enough to drive the global routing
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sky130_fd_sc_hd__buf_4 in_buf (
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.A (A),
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.X (Y) );
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endmodule
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//-----------------------------------------------------
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// Function : A minimum output pad
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//-----------------------------------------------------
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module GPOUT (
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inout Y, // External PAD signal
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input A // Data output
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);
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// Assume a 4x buf is enough to drive the block outside FPGA
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sky130_fd_sc_hd__buf_4 in_buf (
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.A (A),
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.X (Y) );
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endmodule
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