Ganesh Gore 9284bbf8fa [SOFA_CHD] Added OpenFPGA taks and verilog netlist		2020-12-09 00:49:00 -07:00
..
cbx_1__0_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
cbx_1__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
cbx_1__12_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
cby_0__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
cby_1__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
cby_12__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
disable_configurable_memory_outputs.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
disable_configure_ports.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
disable_routing_multiplexer_outputs.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
disable_sb_outputs.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
global_ports.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
logical_tile_clb_mode_clb_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
logical_tile_clb_mode_default__fle.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
logical_tile_io_mode_io_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_0__0_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_0__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_0__12_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_1__0_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_1__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_1__12_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_12__0_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_12__1_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sb_12__12_.sdc	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00