mirror of https://github.com/lnis-uofu/SOFA.git
45 lines
2.8 KiB
Verilog
45 lines
2.8 KiB
Verilog
//-------------------------------------------
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// A file to include all the dependency HDL codes
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// required by Caravel gate-level netlists
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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`define USE_POWER_PINS 1
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
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////////////////////////////////////
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// Skywater standard cell netlists
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// I/O cells
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
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// High density cells
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
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// High voltage cells
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
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`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
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// Gate-level netlists
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/DFFRAM.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/caravel.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/chip_io.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/digital_pll.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/mgmt_core.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_id_programming.v"
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// Use RTL codes for the following module as the gate-level netlists are buggy
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// in handling power pins
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/defines.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect_hv.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/gpio_control_block.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/simple_por.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/user_project_wrapper.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/storage.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/user_proj_example.v"
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`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/sram_1rw1r_32_256_8_sky130.v"
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