mirror of https://github.com/lnis-uofu/SOFA.git
46 lines
2.0 KiB
Markdown
46 lines
2.0 KiB
Markdown
# SOFA
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[](https://github.com/LNIS-Projects/skywater-openfpga/actions)
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[](https://skywater-openfpga.readthedocs.io/en/latest/?badge=latest)
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## Introduction
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SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework
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## Quick Start
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```bash
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#Clone the repository and go inside it
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git clone https://github.com/LNIS-Projects/skywater-openfpga.git
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python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
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```
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---
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* If you have openfpga repository cloned at the same level of this project, you can simple call
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```bash
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python3 SCRIPT/repo_setup.py
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```
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Otherwise, you should provide full path using the option _--openfpga\_root\_path_
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## Directory Organization
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* Keep this folder clean and organized as follows
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- **DOC**: documentation of the project
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- **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
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- **BENCHMARK**: Benchmarks to be tested on the FPGA fabric
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- **HDL**: Hardware description netlists for the FPGA fabrics
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- **SDC**: design constraints
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- **SCRIPT**: Scripts to setup, run OpenFPGA etc.
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- **TESTBENCH**: Verilog testbenches generated by OpenFPGA
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- **PDK**: Technology files linked from skywater opensource pdk
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- **SNPS\_ICC2**: workspace of Synopsys IC Compiler 2
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Keep a README inside the folder about the ICC2 version and how-to-use.
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- **MSIM**: workspace of verification using Mentor ModelSim
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---
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* Note:
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- Please **ONLY** place folders under this directory.
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README should be the **ONLY** file under this directory
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- Each EDA tool should have **independent** workspace in separated directories
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