mirror of https://github.com/lnis-uofu/SOFA.git
163 lines
5.2 KiB
Verilog
163 lines
5.2 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// cavlc_fsm ////
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//// ////
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//// Description ////
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//// controls the cavlc parsing process ////
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//// ////
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//// Author(s): ////
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//// - bin qiu, qiubin@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//2011-8-7 18:57 initial revision
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`include "defines.v"
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module cavlc_fsm
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(
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clk,
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rst_n,
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ena,
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start,
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max_coeff_num,
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TotalCoeff,
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TotalCoeff_comb,
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TrailingOnes,
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TrailingOnes_comb,
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ZeroLeft,
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state,
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i,
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idle,
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valid
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);
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//------------------------
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//ports
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//------------------------
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input clk;
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input rst_n;
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input ena;
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input start;
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input [4:0] max_coeff_num;
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input [4:0] TotalCoeff;
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input [4:0] TotalCoeff_comb;
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input [1:0] TrailingOnes;
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input [1:0] TrailingOnes_comb;
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input [3:0] ZeroLeft;
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output [7:0] state;
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output [3:0] i;
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output idle;
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output valid;
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//------------------------
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//FFs
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//------------------------
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reg [7:0] state;
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reg [3:0] i;
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reg valid;
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//------------------------
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//state & i & valid
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//------------------------
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always @(posedge clk or negedge rst_n)
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if (!rst_n) begin
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state <= `cavlc_idle_s;
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i <= 0;
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valid <= 0;
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end
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else if (ena)
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case(state)
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`cavlc_idle_s : begin
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if (start) begin
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state <= `cavlc_read_total_coeffs_s;
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valid <= 0;
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end
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else begin
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state <= `cavlc_idle_s;
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end
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end
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`cavlc_read_total_coeffs_s : begin
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i <= TotalCoeff_comb -1;
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if (TrailingOnes_comb > 0 && TotalCoeff_comb > 0)
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state <= `cavlc_read_t1s_flags_s;
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else if (TotalCoeff_comb > 0)
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state <= `cavlc_read_level_prefix_s;
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else begin
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state <= `cavlc_idle_s;
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valid <= 1;
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end
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end
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`cavlc_read_t1s_flags_s : begin
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if (TrailingOnes == TotalCoeff)
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state <= `cavlc_read_total_zeros_s;
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else begin
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state <= `cavlc_read_level_prefix_s;
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i <= i - TrailingOnes;
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end
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end
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`cavlc_read_level_prefix_s : begin
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state <= `cavlc_read_level_suffix_s;
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end
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`cavlc_read_level_suffix_s : begin
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state <= `cavlc_calc_level_s;
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end
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`cavlc_calc_level_s : begin
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if ( i == 0 && TotalCoeff < max_coeff_num)
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state <= `cavlc_read_total_zeros_s;
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else if (i == 0) begin
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state <= `cavlc_read_run_befores_s;
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i <= TotalCoeff - 1;
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end
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else begin
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state <= `cavlc_read_level_prefix_s;
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i <= i - 1;
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end
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end
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`cavlc_read_total_zeros_s : begin
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state <= `cavlc_read_run_befores_s;
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i <= TotalCoeff - 1;
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end
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`cavlc_read_run_befores_s : begin
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if (i == 0 || ZeroLeft == 0) begin
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state <= `cavlc_idle_s;
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valid <= 1;
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end
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else begin
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state <= `cavlc_read_run_befores_s;
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i <= i - 1;
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end
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end
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endcase
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assign idle = state[`cavlc_idle_bit];
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endmodule
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