mirror of https://github.com/lnis-uofu/SOFA.git
194 lines
7.7 KiB
Python
194 lines
7.7 KiB
Python
#####################################################################
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# Python script to adapt an OpenFPGA architecture file
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# This script will
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# - Convert the ${SKYWATER_OPENFPGA_HOME} to the absolute path of current directory
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#
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#####################################################################
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import os
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from os.path import dirname, abspath
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import shutil
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import re
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import argparse
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import logging
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG);
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#####################################################################
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# Parse the options
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# - OpenFPGA root path is a manadatory option
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#####################################################################
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parser = argparse.ArgumentParser(description='Generator for technology-mapped wrapper');
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parser.add_argument('--output_verilog',
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default='./temp_wrapper.v',
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help='Specify output verilog file path');
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args = parser.parse_args();
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#####################################################################
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# Define Wishbone interface pin sequence
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# The list start from left-side of the wrapper to the right side
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# Target FPGA gpio start from 135, 134 ...
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#####################################################################
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wishbone_pins = ['wb_rst_i',
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'wbs_ack_o',
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'wbs_cyc_i',
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'wbs_stb_i',
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'wbs_we_i',
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'wbs_adr_i[0]',
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'wbs_dat_i[0]',
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'wbs_dat_o[0]',
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'wbs_sel_i[0]',
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'wbs_adr_i[1]',
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'wbs_dat_i[1]',
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'wbs_dat_o[1]',
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'wbs_sel_i[1]',
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'wbs_adr_i[2]',
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'wbs_dat_i[2]',
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'wbs_dat_o[2]',
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'wbs_sel_i[2]',
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'wbs_adr_i[3]',
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'wbs_dat_i[3]',
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'wbs_dat_o[3]',
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'wbs_sel_i[3]',
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'wbs_adr_i[4]',
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'wbs_dat_i[4]',
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'wbs_dat_o[4]',
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'wbs_adr_i[5]',
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'wbs_dat_i[5]',
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'wbs_dat_o[5]',
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'wbs_adr_i[6]',
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'wbs_dat_i[6]',
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'wbs_dat_o[6]',
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'wbs_adr_i[7]',
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'wbs_dat_i[7]',
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'wbs_dat_o[7]',
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'wbs_adr_i[8]',
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'wbs_dat_i[8]',
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'wbs_dat_o[8]',
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'wbs_adr_i[9]',
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'wbs_dat_i[9]',
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'wbs_dat_o[9]',
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'wbs_adr_i[10]',
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'wbs_dat_i[10]',
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'wbs_dat_o[10]',
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'wbs_adr_i[11]',
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'wbs_dat_i[11]',
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'wbs_dat_o[11]',
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'wbs_adr_i[12]',
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'wbs_dat_i[12]',
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'wbs_dat_o[12]',
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'wbs_adr_i[13]',
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'wbs_dat_i[13]',
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'wbs_dat_o[13]',
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'wbs_adr_i[14]',
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'wbs_dat_i[14]',
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'wbs_dat_o[14]',
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'wbs_adr_i[15]',
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'wbs_dat_i[15]',
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'wbs_dat_o[15]',
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'wbs_adr_i[16]',
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'wbs_dat_i[16]',
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'wbs_dat_o[16]',
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'wbs_adr_i[17]',
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'wbs_dat_i[17]',
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'wbs_dat_o[17]',
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'wbs_adr_i[18]',
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'wbs_dat_i[18]',
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'wbs_dat_o[18]',
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'wbs_adr_i[19]',
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'wbs_dat_i[19]',
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'wbs_dat_o[19]',
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'wbs_adr_i[20]',
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'wbs_dat_i[20]',
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'wbs_dat_o[20]',
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'wbs_adr_i[21]',
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'wbs_dat_i[21]',
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'wbs_dat_o[21]',
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'wbs_adr_i[22]',
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'wbs_dat_i[22]',
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'wbs_dat_o[22]',
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'wbs_adr_i[23]',
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'wbs_dat_i[23]',
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'wbs_dat_o[23]',
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'wbs_adr_i[24]',
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'wbs_dat_i[24]',
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'wbs_dat_o[24]',
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'wbs_adr_i[25]',
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'wbs_dat_i[25]',
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'wbs_dat_o[25]',
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'wbs_adr_i[26]',
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'wbs_dat_i[26]',
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'wbs_dat_o[26]',
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'wbs_adr_i[27]',
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'wbs_dat_i[27]',
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'wbs_dat_o[27]',
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'wbs_adr_i[28]',
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'wbs_dat_i[28]',
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'wbs_dat_o[28]',
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'wbs_adr_i[29]',
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'wbs_dat_i[29]',
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'wbs_dat_o[29]',
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'wbs_adr_i[30]',
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'wbs_dat_i[30]',
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'wbs_dat_o[30]',
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'wbs_adr_i[31]',
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'wbs_dat_i[31]',
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'wbs_dat_o[31]'
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];
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#####################################################################
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# Define Logic Analyzer interface pin sequence
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# The list start from left-side of the wrapper to the right side
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# Target FPGA gpio start from 135, 134 ...
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#####################################################################
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logic_analyzer_pins = [];
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for ipin in range(13, 128):
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logic_analyzer_pins.append(["la_data_in[" + str(ipin) + "]", "la_data_out[" + str(ipin) + "]", "la_oen[" + str(ipin) + "]"]);
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#####################################################################
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# Generate wrapper lines
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#####################################################################
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logging.info("Outputting HDL codes to " + str(args.output_verilog) + " ...");
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vlog_file = open(args.output_verilog, "a");
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num_wishbone_pins = len(wishbone_pins);
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num_logic_analyzer_pins = len(logic_analyzer_pins);
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num_gpio_pins = 135 - 21 + 1;
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print("Number of Wishbone pins: " + str(num_wishbone_pins));
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print("Number of logic analyzer pins: " + str(num_logic_analyzer_pins));
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print("Number of gpio pins: " + str(num_gpio_pins));
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assert num_wishbone_pins < num_logic_analyzer_pins;
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assert num_logic_analyzer_pins == num_gpio_pins;
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for ipin in range(0, num_gpio_pins):
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curr_line = "";
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if ((ipin < num_wishbone_pins) and (ipin < num_logic_analyzer_pins)):
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# If this is an input pin of wishbone interface, whose postfix is '_i', we use MUX
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# otherwise, this is an output pin, we just wire the input to logic analyzer
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if ((wishbone_pins[ipin].endswith("_i")) or (re.search(r'_i\[\d+\]$', wishbone_pins[ipin], re.M|re.I))):
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curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(la_wb_switch), .A1(" + str(wishbone_pins[ipin]) + "), .A0(" + str(logic_analyzer_pins[ipin][0]) + "), .X(gfpga_pad_EMBEDDED_IO_SOC_IN[" + str(135 - ipin) + "]));";
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vlog_file.write(curr_line + "\n");
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curr_line = " " + "assign " + str(logic_analyzer_pins[ipin][1]) + " = gfpga_pad_EMBEDDED_IO_SOC_OUT[" + str(135 - ipin) + "];";
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vlog_file.write(curr_line + "\n");
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elif ((wishbone_pins[ipin].endswith("_o")) or (re.search(r'_o\[\d+\]$', wishbone_pins[ipin], re.M|re.I))):
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curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_SOC_IN[" + str(135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";";
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vlog_file.write(curr_line + "\n");
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curr_line = " " + "assign " + str(wishbone_pins[ipin]) + " = gfpga_pad_EMBEDDED_IO_SOC_OUT[" + str(135 - ipin) + "];";
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vlog_file.write(curr_line + "\n");
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elif ((ipin >= num_wishbone_pins) and (ipin < num_logic_analyzer_pins)):
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curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_SOC_IN[" + str(135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";";
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vlog_file.write(curr_line + "\n");
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curr_line = " " + "assign " + str(logic_analyzer_pins[ipin][1]) + " = gfpga_pad_EMBEDDED_IO_SOC_OUT[" + str(135 - ipin) + "];";
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vlog_file.write(curr_line + "\n");
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vlog_file.close();
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logging.info("Done");
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