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SOFA/ARCH/openfpga_arch_template
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tangxifan e7fd8e7d92 [Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist 2020-12-09 12:12:40 -07:00
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README.md [Documentation] Add README for subdirectories 2020-10-09 22:36:43 -06:00
k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml [Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point 2020-11-18 11:56:22 -07:00
k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml [Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA 2020-11-30 17:58:56 -07:00
k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml [Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist 2020-12-09 12:12:40 -07:00
k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml [Arch] Patch reset port name to be consistent with post-PnR netlist 2020-12-02 13:46:40 -07:00
k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml modify carry chain to change output mux 2020-11-30 07:08:09 -08:00

README.md

Naming convention for OpenFPGA architecture files

Please reveal the following architecture features in the names to help quickly spot architecture files. Note that an OpenFPGA architecture can be applied to multiple VPR architecture files.

  • k<lut_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
  • frac: If fracturable LUT is used or not.
  • N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
  • adder_chain: If hard adder/carry chain is used inside CLBs
  • register_chain: If shift register chain is used inside CLBs
  • scan_chain: If scan chain testing infrastructure is used inside CLBs
  • mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
  • aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
  • <bank|cc|frame|standalone>: specify the type of configuration protocol used in the architecture.
    • bank refers to the memory bank
    • cc refers to the configuration chain
    • frame refers to the frame-based organization
    • standalone referes to the vanilla organization
  • fixed_sim: fixed clock frequencies in simulation settings. If auto clock frequencies are used, there is no need to appear in the naming
  • intermediate buffer: If intermediate buffers are used in LUT designs.
  • behavioral: If behavioral Verilog modeling is specified
  • local_encoder: If local encoders are used in routing multiplexer design
  • spyio/spypad: If spy I/Os are used
  • stdcell: If circuit designs are built with standard cells only
  • tree_mux: If routing multiplexers are built with a tree-like structure
  • <feature_size>: The technology node which the delay numbers are extracted from.
  • powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.

Other features are used in naming should be listed here.