History

tangxifan 1eac22feba [Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration		2020-12-18 20:18:02 -07:00
..
caravel_dv	[Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration	2020-12-18 20:18:02 -07:00
common	[Testbench] Add power pin support to scff testbench	2020-12-18 15:55:05 -07:00
digital_io_hd_test	[Testbench] Restore post-Pnr testbenches for CHD version	2020-12-14 13:17:37 -07:00
k4_N8_caravel_io_FPGA_12x12_fdhd_cc	[Testbench] Rename testbench to be consistent with post-PnR netlist path change	2020-12-14 20:27:22 -07:00
k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench	[Testbench] Bug fix for wrapper testbench include netlist	2020-12-14 13:30:01 -07:00
k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench	[Testbench] Bug fix in using power pins	2020-12-18 17:49:16 -07:00
README.md	[Doc] Add documentation about the testbenches	2020-11-20 13:59:15 -07:00

README.md

Skywater PDK

This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric. Please keep this directory clean and organize as follows:

Each testbench should be placed in a separated directory
common: include commonly used testbench template for post-PnR verification mainly
READMD is the only file allowed in the directory, others should be sub-directories.