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tangxifan a900cba5a5 [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
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common [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
README.md [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA. It also includes necessary wrappers to enable the netlist generation. The custom netlists are place in the common directory.