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tangxifan 31dcd4a17f [HDL] Add a wrapper for HD MUX2 cell required by carry logic 2020-11-27 16:01:27 -07:00
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common [HDL] Add a wrapper for HD MUX2 cell required by carry logic 2020-11-27 16:01:27 -07:00
README.md [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA. It also includes necessary wrappers to enable the netlist generation. The custom netlists are place in the common directory.