mirror of https://github.com/lnis-uofu/SOFA.git
86 lines
3.1 KiB
Tcl
86 lines
3.1 KiB
Tcl
#####################################################################
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# A template script to report timing for Connection Blocks from post-PnR results
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# using Synopsys PrimeTime
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#####################################################################
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#
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##################################
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# Define environment variables
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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#set DEVICE_NAME "SOFA_HD"
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set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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# Enable preprocessing in Verilog parser
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set_app_var svr_enable_vpp true
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# Enable reporting ALL the timing paths even those are NOT constrained
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set_app_var timing_report_unconstrained_paths true
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set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm"
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set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
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set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
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##################################
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# Sweep all the CB design
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set DESIGN_NAMES {"cbx_1__0_" "cbx_1__1_" "cbx_1__2_" "cby_0__1_" "cby_1__1_" "cby_2__1_"};
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foreach DESIGN_NAME ${DESIGN_NAMES} {
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##################################
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# Ensure a clean start
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remove_design -all
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remove_lib -all
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##################################
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# Read timing libraries
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read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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##################################
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# Read post-PnR netlists
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read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
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link_design ${DESIGN_NAME}
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#########################################
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# Setup constraints to break combinational loops
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#source ${SDC_HOME}/disable_configurable_memory_outputs.sdc
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set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
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#########################################
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# Setup constraints for clocks
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#source ${SDC_HOME}/global_ports.sdc
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#########################################
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# Setup constraints for paths
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# Connection block name
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set CB_CHAN_NAME "chan*";
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set CB_PIN_NAME "*grid_pin*";
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set_max_delay -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} 6.02e-11
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set_max_delay -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} 6.02e-11
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##################################
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# Read post-PnR parasitics
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read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
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##################################
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# Report timing of Connect block
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report_timing -from ${CB_CHAN_NAME} -to ${CB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
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report_timing -from ${CB_CHAN_NAME} -to ${CB_PIN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
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}
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##################################
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# Finish and quit
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# Comment it out if you want to debug
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exit
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