History

tangxifan ed92cba451 [HDL] Add netlist for simulation with Caravel + FPGA		2020-12-08 15:35:38 -07:00
..
common	[HDL] Add netlist for simulation with Caravel + FPGA	2020-12-08 15:35:38 -07:00
k4_N8_caravel_io_FPGA_12x12_fdhd_cc	[Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants	2020-12-02 15:22:19 -07:00
k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench	[Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants	2020-12-02 15:22:19 -07:00
README.md	[Doc] Add documentation about the testbenches	2020-11-20 13:59:15 -07:00

README.md

Skywater PDK

This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric. Please keep this directory clean and organize as follows:

Each testbench should be placed in a separated directory
common: include commonly used testbench template for post-PnR verification mainly
READMD is the only file allowed in the directory, others should be sub-directories.