mirror of https://github.com/lnis-uofu/SOFA.git
129 lines
3.3 KiB
Verilog
129 lines
3.3 KiB
Verilog
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`timescale 1ns / 10ps
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module SystemClockControl (
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OperatingClockRef_i,
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Clock32KIn_i,
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SPIClock_i,
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ResetIn_i,
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FfeClkSelect_i,
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SmClkSelect_i,
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SmSpeedSelect_i,
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SpiClkSelect_i,
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ClkSourceSelect_i,
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Clk32KhzEnable_i,
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MainClkEnable_i,
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FfeClkEnable_i,
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CM_AutoDrain_Busy,
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SmClock_o,
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FfeClock_o,
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FfeClock_x2_o,
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clock_32KHz_o,
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multiplierClk_o,
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ClockGen_State_o,
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CM_FIFO_ReadClk,
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clk_ringosc_i,
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clk_ringosc_x2_i,
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enable_i,
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clk_cal_value_o,
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assp_ringosc_en_o
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);
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// IO Declaration
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input OperatingClockRef_i;
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input Clock32KIn_i;
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input SPIClock_i;
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input ResetIn_i;
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input [2:0] FfeClkSelect_i;
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input [2:0] SmClkSelect_i;
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input SmSpeedSelect_i;
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input SpiClkSelect_i;
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input ClkSourceSelect_i;
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input Clk32KhzEnable_i;
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input MainClkEnable_i;
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input FfeClkEnable_i;
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input CM_AutoDrain_Busy;
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output SmClock_o;
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output FfeClock_o;
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output FfeClock_x2_o;
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output clock_32KHz_o;
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output multiplierClk_o;
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output [3:0] ClockGen_State_o;
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output CM_FIFO_ReadClk;
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input clk_ringosc_i;
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input clk_ringosc_x2_i;
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input enable_i;
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output [15:0] clk_cal_value_o;
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output assp_ringosc_en_o;
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reg multiplierClk_o;
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wire [3:0] ClockGen_State_o;
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wire CM_FIFO_ReadClk;
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wire assp_ringosc_en_o;
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// Internal Signals Declaration
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wire highSpeedClock, highSpeedClock_buff, highSpeedClock_x2_buff;
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reg [6:0] ClockDiv;
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wire FfeClock;
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reg SmClock;
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wire RingOscEnable;
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wire ring_osc_clk;
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wire OperatingClockRef;
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// Operations
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// Gating the enternal osc
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// assign OperatingClockRef = OperatingClockRef_i && MainClkEnable_i;
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assign OperatingClockRef = OperatingClockRef_i;
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// CM FIFO AutoDrain Read Clock
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// assign CM_FIFO_ReadClk = CM_AutoDrain_Busy ? (FfeClock && FfeClkEnable_i): SPIClock_i;
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assign CM_FIFO_ReadClk = CM_AutoDrain_Busy ? highSpeedClock_buff : SPIClock_i;
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// Ring Osclilator enable when the when weither FFE or SM is busy
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// assign RingOscEnable = !ResetIn_i && MainClkEnable_i && ClkSourceSelect_i;
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// Logic to gate 32KHz clock when the ULPSH goes to sleep
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// Only static power consumption
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assign clock_32KHz_o = Clock32KIn_i && Clk32KhzEnable_i;
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// Logic to select between the external high speed clock and the internal ring oscillation
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// and main clock division
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// assign highSpeedClock = ClkSourceSelect_i ? ring_osc_clk : OperatingClockRef;
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buff buff_highSpeedClock (.A(clk_ringosc_i), .Q(highSpeedClock_buff)); // don't use a clock network for this
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//pragma attribute buff_highSpeedClock dont_touch true
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buff buff_highSpeedClock_x2 (.A(clk_ringosc_x2_i), .Q(highSpeedClock_x2_buff)); // don't use a clock network for this
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//pragma attribute buff_highSpeedClock_x2 dont_touch true
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// FFE CLK and SM CLK select and masking
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// assign FfeClock_o = SpiClkSelect_i ? SPIClock_i : FfeClock && FfeClkEnable_i;
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// assign SmClock_o = SmSpeedSelect_i ? SmClock : (SpiClkSelect_i ? SPIClock_i : FfeClock);
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assign FfeClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;
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assign FfeClock_x2_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_x2_buff;
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assign SmClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;
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ring_osc_adjust ring_osc_adjust_1 (
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.reset_i ( ResetIn_i ),
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.clk_ringosc_i ( clk_ringosc_i ),
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.clk_32khz_i ( Clock32KIn_i ),
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.enable_i ( enable_i ),
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.cal_val_o ( clk_cal_value_o )
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);
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assign assp_ringosc_en_o = ClkSourceSelect_i || MainClkEnable_i;
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endmodule
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