mirror of https://github.com/lnis-uofu/SOFA.git
111 lines
3.2 KiB
Verilog
111 lines
3.2 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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// Created by SmartDesign Tue Jan 16 17:22:21 2018
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// Version: v11.8 11.8.0.26
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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// TOP_multi_enc_decx2x4
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module multi_enc_decx2x4(
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// Inputs
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clock,
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datain,
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datain1,
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datain1_0,
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datain_0,
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reset,
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// Outputs
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dataout,
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dataout1,
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dataout1_0,
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dataout_0
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);
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//--------------------------------------------------------------------
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// Input
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//--------------------------------------------------------------------
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input clock;
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input [127:0] datain;
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input [127:0] datain1;
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input [127:0] datain1_0;
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input [127:0] datain_0;
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input reset;
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//--------------------------------------------------------------------
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// Output
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//--------------------------------------------------------------------
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output [127:0] dataout;
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output [127:0] dataout1;
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output [127:0] dataout1_0;
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output [127:0] dataout_0;
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//--------------------------------------------------------------------
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// Nets
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//--------------------------------------------------------------------
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wire clock;
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wire [127:0] datain;
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wire [127:0] datain1;
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wire [127:0] datain1_0;
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wire [127:0] datain_0;
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wire [127:0] dataout_net_0;
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wire [127:0] dataout1_net_0;
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wire [127:0] dataout1_0_net_0;
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wire [127:0] dataout_0_net_0;
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wire reset;
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wire [127:0] top_0_dataout;
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wire [127:0] top_1_dataout1;
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wire [127:0] dataout_net_1;
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wire [127:0] dataout1_net_1;
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wire [127:0] dataout1_0_net_1;
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wire [127:0] dataout_0_net_1;
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//--------------------------------------------------------------------
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// Top level output port assignments
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//--------------------------------------------------------------------
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assign dataout_net_1 = dataout_net_0;
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assign dataout[127:0] = dataout_net_1;
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assign dataout1_net_1 = dataout1_net_0;
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assign dataout1[127:0] = dataout1_net_1;
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assign dataout1_0_net_1 = dataout1_0_net_0;
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assign dataout1_0[127:0] = dataout1_0_net_1;
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assign dataout_0_net_1 = dataout_0_net_0;
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assign dataout_0[127:0] = dataout_0_net_1;
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//--------------------------------------------------------------------
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// Component instances
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//--------------------------------------------------------------------
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//--------top
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top top_0(
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// Inputs
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.clock ( clock ),
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.reset ( reset ),
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.datain ( datain ),
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.datain1 ( datain1 ),
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// Outputs
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.dataout ( top_0_dataout ),
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.dataout1 ( dataout1_0_net_0 )
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);
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//--------top
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top top_1(
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// Inputs
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.clock ( clock ),
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.reset ( reset ),
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.datain ( datain_0 ),
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.datain1 ( datain1_0 ),
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// Outputs
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.dataout ( dataout_0_net_0 ),
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.dataout1 ( top_1_dataout1 )
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);
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//--------top
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top top_2(
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// Inputs
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.clock ( clock ),
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.reset ( reset ),
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.datain ( top_0_dataout ),
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.datain1 ( top_1_dataout1 ),
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// Outputs
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.dataout ( dataout_net_0 ),
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.dataout1 ( dataout1_net_0 )
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);
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endmodule
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