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tangxifan 8803b30b26 [HDL] Rename por of I/O cell to be consistent with documentation 2020-11-17 19:33:53 -07:00
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common [HDL] Rename por of I/O cell to be consistent with documentation 2020-11-17 19:33:53 -07:00
README.md [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA. It also includes necessary wrappers to enable the netlist generation. The custom netlists are place in the common directory.